nvsram.h

Go to the documentation of this file.

/****************************************************************************
** Copyright (C) 2020 MikroElektronika d.o.o.
** Contact: https://www.mikroe.com/contact
**
** Permission is hereby granted, free of charge, to any person obtaining a copy
** of this software and associated documentation files (the "Software"), to deal
** in the Software without restriction, including without limitation the rights
** to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
** copies of the Software, and to permit persons to whom the Software is
** furnished to do so, subject to the following conditions:
** The above copyright notice and this permission notice shall be
** included in all copies or substantial portions of the Software.
**
** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
**  USE OR OTHER DEALINGS IN THE SOFTWARE.
****************************************************************************/
 
#ifndef NVSRAM_H
#define NVSRAM_H
 
#ifdef __cplusplus
extern "C"{
#endif
 
#ifdef PREINIT_SUPPORTED
#include "preinit.h"
#endif
 
#ifdef MikroCCoreVersion
    #if MikroCCoreVersion >= 1
        #include "delays.h"
    #endif
#endif
 
#include "drv_digital_out.h"
#include "drv_digital_in.h"
#include "drv_i2c_master.h"
 
#define NVSRAM_MEM_CTL_REG             0x00
#define NVSRAM_SERIAL_NUM_REG_1        0x01
#define NVSRAM_SERIAL_NUM_REG_2        0x02
#define NVSRAM_SERIAL_NUM_REG_3        0x03
#define NVSRAM_SERIAL_NUM_REG_4        0x04
#define NVSRAM_SERIAL_NUM_REG_5        0x05
#define NVSRAM_SERIAL_NUM_REG_6        0x06
#define NVSRAM_SERIAL_NUM_REG_7        0x07
#define NVSRAM_SERIAL_NUM_REG_8        0x08
#define NVSRAM_DEV_ID_REG_1            0x09
#define NVSRAM_DEV_ID_REG_2            0x0A
#define NVSRAM_DEV_ID_REG_3            0x0B
#define NVSRAM_DEV_ID_REG_4            0x0C
#define NVSRAM_CMD_REG                 0xAA
 
 // nvsram_reg
 
#define NVSRAM_I2C_MEM_SEL             0x50
 
#define NVSRAM_CMD_STORE               0x3C
#define NVSRAM_CMD_RECALL              0x60
#define NVSRAM_CMD_ASENB               0x59
#define NVSRAM_CMD_ASDISB              0x19
#define NVSRAM_CMD_SLEEP               0xB9
 
#define NVSRAM_BP_NONE                 0x00
#define NVSRAM_BP_QUARTER              0x04
#define NVSRAM_BP_HALF                 0x08
#define NVSRAM_BP_ALL                  0x0C
#define NVSRAM_NO_SNL                  0x00
#define NVSRAM_SNL                     0x40
 
#define NVSRAM_WRITE_MEMORY_DISABLE    0x00
#define NVSRAM_WRITE_MEMORY_ENABLE     0x01
 
#define NVSRAM_I2C_SLAVE_ADDR_0        0x18
#define NVSRAM_I2C_SLAVE_ADDR_1        0x1A
#define NVSRAM_I2C_SLAVE_ADDR_2        0x1C
#define NVSRAM_I2C_SLAVE_ADDR_3        0x1E
 
 // nvsram_set
 
#define NVSRAM_MAP_MIKROBUS( cfg, mikrobus ) \
    cfg.scl = MIKROBUS( mikrobus, MIKROBUS_SCL ); \
    cfg.sda = MIKROBUS( mikrobus, MIKROBUS_SDA ); \
    cfg.wp = MIKROBUS( mikrobus, MIKROBUS_PWM )
 
 // nvsram_map
 // nvsram
 
typedef struct
{
    // Output pins
    digital_out_t  wp;                               
    // Modules
    i2c_master_t i2c;                                
    // I2C slave address
    uint8_t slave_address;                           
} nvsram_t;
 
typedef struct
{
    pin_name_t  scl;        
    pin_name_t  sda;        
    pin_name_t  wp;         
    uint32_t  i2c_speed;                                
    uint8_t   i2c_address;                              
} nvsram_cfg_t;
 
typedef enum
{
   NVSRAM_OK = 0,
   NVSRAM_ERROR = -1
 
} nvsram_return_value_t;
 
void nvsram_cfg_setup ( nvsram_cfg_t *cfg );
 
err_t nvsram_init ( nvsram_t *ctx, nvsram_cfg_t *cfg );
 
err_t nvsram_generic_write ( nvsram_t *ctx, uint8_t reg, uint8_t *tx_buf, uint8_t tx_len );
 
err_t nvsram_generic_read ( nvsram_t *ctx, uint8_t reg, uint8_t *rx_buf, uint8_t rx_len );
 
void nvsram_reg_write ( nvsram_t *ctx, uint8_t reg, uint8_t tx_data );
 
uint8_t nvsram_reg_read ( nvsram_t *ctx, uint8_t reg );
 
void nvsram_burst_reg_write ( nvsram_t *ctx, uint8_t reg, uint8_t *p_tx_data, uint8_t n_bytes );
 
void nvsram_burst_reg_read ( nvsram_t *ctx, uint8_t reg, uint8_t *p_rx_data, uint8_t n_bytes );
 
void nvsram_send_cmd ( nvsram_t *ctx, uint8_t cmd );
 
uint32_t nvsram_read_dev_id ( nvsram_t *ctx );
 
void nvsram_memory_write ( nvsram_t *ctx, uint32_t mem_adr, uint8_t *p_tx_data, uint16_t n_bytes );
 
void nvsram_memory_read ( nvsram_t *ctx, uint32_t mem_adr, uint8_t *p_rx_data, uint16_t n_bytes );
 
void nvsram_enable_memory_write ( nvsram_t *ctx, uint8_t en_wr_mem );
 
#ifdef __cplusplus
}
#endif
#endif // NVSRAM_H
 
 // nvsram
 
// ------------------------------------------------------------------------ END