Settings for registers of nvSRAM 3 Click driver. More...

Macros
#define	NVSRAM3_SERIAL_NUMBER_LOCK 0x40
	nvSRAM 3 Control Registers description setting.

#define	NVSRAM3_SERIAL_NUMBER_UNLOCK 0x00

#define	NVSRAM3_BLOCK_PROTECT_QUARTER 0x04

#define	NVSRAM3_BLOCK_PROTECT_HALF 0x08

#define	NVSRAM3_BLOCK_PROTECT_FULL 0x0C

#define	NVSRAM3_STORE_COMMAND 0x3C

#define	NVSRAM3_RECALL_COMMAND 0x60

#define	NVSRAM3_ASENB_COMMAND 0x59

#define	NVSRAM3_ASDISB_COMMAND 0x19

#define	NVSRAM3_SLEEP_COMMAND 0xB9

#define	NVSRAM3_RTC_WRITE_ENABLE 0x02
	nvSRAM 3 RTC Registers description setting.

#define	NVSRAM3_RTC_WRITE_DISABLE 0x00

#define	NVSRAM3_RTC_READ_ENABLE 0x01

#define	NVSRAM3_RTC_READ_DISABLE 0x00

#define	NVSRAM3_MEMORY_DEV_ADDR_0 0x50
	nvSRAM 3 device address setting.

#define	NVSRAM3_MEMORY_DEV_ADDR_1 0x52

#define	NVSRAM3_MEMORY_DEV_ADDR_2 0x54

#define	NVSRAM3_MEMORY_DEV_ADDR_3 0x56

#define	NVSRAM3_RTC_DEV_ADDR_0 0x68

#define	NVSRAM3_RTC_DEV_ADDR_1 0x6A

#define	NVSRAM3_RTC_DEV_ADDR_2 0x6C

#define	NVSRAM3_RTC_DEV_ADDR_3 0x6E

#define	NVSRAM3_CONTROL_DEV_ADDR_0 0x18

#define	NVSRAM3_CONTROL_DEV_ADDR_1 0x1A

#define	NVSRAM3_CONTROL_DEV_ADDR_2 0x1C

#define	NVSRAM3_CONTROL_DEV_ADDR_3 0x1E

#define	NVSRAM3_HSB_ENABLE 0x00
	nvSRAM 3 pins setting.

#define	NVSRAM3_HSB_DISABLE 0x01

#define	NVSRAM3_WP_ENABLE 0x00

#define	NVSRAM3_WP_DISABLE 0x01

Detailed Description

Settings for registers of nvSRAM 3 Click driver.

Macro Definition Documentation

◆ NVSRAM3_ASDISB_COMMAND

#define NVSRAM3_ASDISB_COMMAND 0x19

◆ NVSRAM3_ASENB_COMMAND

#define NVSRAM3_ASENB_COMMAND 0x59

◆ NVSRAM3_BLOCK_PROTECT_FULL

#define NVSRAM3_BLOCK_PROTECT_FULL 0x0C

◆ NVSRAM3_BLOCK_PROTECT_HALF

#define NVSRAM3_BLOCK_PROTECT_HALF 0x08

◆ NVSRAM3_BLOCK_PROTECT_QUARTER

#define NVSRAM3_BLOCK_PROTECT_QUARTER 0x04

◆ NVSRAM3_CONTROL_DEV_ADDR_0

#define NVSRAM3_CONTROL_DEV_ADDR_0 0x18

◆ NVSRAM3_CONTROL_DEV_ADDR_1

#define NVSRAM3_CONTROL_DEV_ADDR_1 0x1A

◆ NVSRAM3_CONTROL_DEV_ADDR_2

#define NVSRAM3_CONTROL_DEV_ADDR_2 0x1C

◆ NVSRAM3_CONTROL_DEV_ADDR_3

#define NVSRAM3_CONTROL_DEV_ADDR_3 0x1E

◆ NVSRAM3_HSB_DISABLE

#define NVSRAM3_HSB_DISABLE 0x01

◆ NVSRAM3_HSB_ENABLE

#define NVSRAM3_HSB_ENABLE 0x00

nvSRAM 3 pins setting.

Specified setting for HSB and WP pins.

◆ NVSRAM3_MEMORY_DEV_ADDR_0

#define NVSRAM3_MEMORY_DEV_ADDR_0 0x50

nvSRAM 3 device address setting.

Specified setting for device slave address selection of nvSRAM 3 Click driver.

◆ NVSRAM3_MEMORY_DEV_ADDR_1

#define NVSRAM3_MEMORY_DEV_ADDR_1 0x52

◆ NVSRAM3_MEMORY_DEV_ADDR_2

#define NVSRAM3_MEMORY_DEV_ADDR_2 0x54

◆ NVSRAM3_MEMORY_DEV_ADDR_3

#define NVSRAM3_MEMORY_DEV_ADDR_3 0x56

◆ NVSRAM3_RECALL_COMMAND

#define NVSRAM3_RECALL_COMMAND 0x60

◆ NVSRAM3_RTC_DEV_ADDR_0

#define NVSRAM3_RTC_DEV_ADDR_0 0x68

◆ NVSRAM3_RTC_DEV_ADDR_1

#define NVSRAM3_RTC_DEV_ADDR_1 0x6A

◆ NVSRAM3_RTC_DEV_ADDR_2

#define NVSRAM3_RTC_DEV_ADDR_2 0x6C

◆ NVSRAM3_RTC_DEV_ADDR_3

#define NVSRAM3_RTC_DEV_ADDR_3 0x6E

◆ NVSRAM3_RTC_READ_DISABLE

#define NVSRAM3_RTC_READ_DISABLE 0x00

◆ NVSRAM3_RTC_READ_ENABLE

#define NVSRAM3_RTC_READ_ENABLE 0x01

◆ NVSRAM3_RTC_WRITE_DISABLE

#define NVSRAM3_RTC_WRITE_DISABLE 0x00

◆ NVSRAM3_RTC_WRITE_ENABLE

#define NVSRAM3_RTC_WRITE_ENABLE 0x02

nvSRAM 3 RTC Registers description setting.

Specified setting for description of nvSRAM 3 Click driver.

◆ NVSRAM3_SERIAL_NUMBER_LOCK

#define NVSRAM3_SERIAL_NUMBER_LOCK 0x40

nvSRAM 3 Control Registers description setting.