nvsram4.h

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/****************************************************************************
** Copyright (C) 2020 MikroElektronika d.o.o.
** Contact: https://www.mikroe.com/contact
**
** Permission is hereby granted, free of charge, to any person obtaining a copy
** of this software and associated documentation files (the "Software"), to deal
** in the Software without restriction, including without limitation the rights
** to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
** copies of the Software, and to permit persons to whom the Software is
** furnished to do so, subject to the following conditions:
** The above copyright notice and this permission notice shall be
** included in all copies or substantial portions of the Software.
**
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** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
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****************************************************************************/
 
#ifndef NVSRAM4_H
#define NVSRAM4_H
 
#ifdef __cplusplus
extern "C"{
#endif
 
#ifdef PREINIT_SUPPORTED
#include "preinit.h"
#endif
 
#ifdef MikroCCoreVersion
    #if MikroCCoreVersion >= 1
        #include "delays.h"
    #endif
#endif
 
#include "drv_digital_out.h"
#include "drv_digital_in.h"
#include "drv_spi_master.h"
 
#define NVSRAM4_STATUS_RDY                                         0x01
#define NVSRAM4_STATUS_WEN                                         0x02
#define NVSRAM4_STATUS_BP0                                         0x04
#define NVSRAM4_STATUS_BP1                                         0x08
#define NVSRAM4_STATUS_SNL                                         0x40
#define NVSRAM4_STATUS_WPEN                                        0x80
    
#define NVSRAM4_RTC_FLAGS                                          0x00
#define NVSRAM4_RTC_TK_CENTURIES                                   0x01
#define NVSRAM4_RTC_ALARM_SECONDS                                  0x02
#define NVSRAM4_RTC_ALARM_MINUTES                                  0x03
#define NVSRAM4_RTC_ALARM_HOURS                                    0x04
#define NVSRAM4_RTC_ALARM_DAY                                      0x05
#define NVSRAM4_RTC_INTERRUPT_STATUS                               0x06
#define NVSRAM4_RTC_WATCHDOG_TIMER                                 0x07
#define NVSRAM4_RTC_CALIBRATION                                    0x08
#define NVSRAM4_RTC_TK_SECONDS                                     0x09
#define NVSRAM4_RTC_TK_MINUTES                                     0x0A
#define NVSRAM4_RTC_TK_HOURS                                       0x0B
#define NVSRAM4_RTC_TK_DAY                                         0x0C
#define NVSRAM4_RTC_TK_DATE                                        0x0D
#define NVSRAM4_RTC_TK_MONTHS                                      0x0E
#define NVSRAM4_RTC_TK_YEARS                                       0x0F
 
 // nvsram4_reg
 
#define NVSRAM4_STATUS_RDSR                                        0x05
#define NVSRAM4_STATUS_FRDSR                                       0x0A
#define NVSRAM4_STATUS_WRSR                                        0x01
#define NVSRAM4_STATUS_WREN                                        0x06
#define NVSRAM4_STATUS_WRDI                                        0x04
 
 // status_reg
 
#define NVSRAM4_SRAM_READ                                          0x03
#define NVSRAM4_SRAM_FREAD                                         0x0B
#define NVSRAM4_SRAM_WRITE                                         0x02
 
 // sram_cmd
 
#define NVSRAM4_SRAM_RDRTC                                         0x13
#define NVSRAM4_SRAM_FAST_RDRTC                                    0x1D
#define NVSRAM4_SRAM_WRTC                                          0x12
 
 // rtc_cmd
 
#define NVSRAM4_SPEC_NV_STORE                                      0x3C
#define NVSRAM4_SPEC_NV_RECALL                                     0x60
#define NVSRAM4_SPEC_NV_ASENB                                      0x59
#define NVSRAM4_SPEC_NV_ASDISB                                     0x19
 
 // nv_spc_cmd
 
#define NVSRAM4_SPEC_SLEEP                                         0xB9
#define NVSRAM4_SPEC_WRSN                                          0xC2
#define NVSRAM4_SPEC_RDSN                                          0xC3
#define NVSRAM4_SPEC_FRDSN                                         0xC9
#define NVSRAM4_SPEC_RDID                                          0x9F
#define NVSRAM4_SPEC_FRDID                                         0x99
 
 // spc_cmd
 
#define NVSRAM4_STATUS_RDY                                         0x01
#define NVSRAM4_STATUS_WEN                                         0x02
#define NVSRAM4_STATUS_BP0                                         0x04
#define NVSRAM4_STATUS_BP1                                         0x08
#define NVSRAM4_STATUS_SNL                                         0x40
#define NVSRAM4_STATUS_WPEN                                        0x80
 
 // status_reg_cont
 
#define NVSRAM4_HOLD_ENABLE                                        0x00
#define NVSRAM4_HOLD_DISABLE                                       0x01
 
 
 // en_hold
 
#define NVSRAM4_HSB_ENABLE                                        0x00
#define NVSRAM4_HSB_DISABLE                                       0x01
 
 
 // en_hw_store
 
#define NVSRAM4_WP_ENABLE                                        0x00
#define NVSRAM4_WP_DISABLE                                       0x01
 
 
 // en_hw_store
 
 
 // nvsram4_set
 
#define NVSRAM4_SUCCESS            0
#define NVSRAM4_ERROR             -1
 
 
 // status
 
#define NVSRAM4_MAP_MIKROBUS( cfg, mikrobus )       \
    cfg.miso = MIKROBUS( mikrobus, MIKROBUS_MISO ); \
    cfg.mosi = MIKROBUS( mikrobus, MIKROBUS_MOSI ); \
    cfg.sck  = MIKROBUS( mikrobus, MIKROBUS_SCK );  \
    cfg.cs   = MIKROBUS( mikrobus, MIKROBUS_CS );   \
    cfg.hld = MIKROBUS( mikrobus, MIKROBUS_AN );    \
    cfg.hsb = MIKROBUS( mikrobus, MIKROBUS_RST );   \
    cfg.wp = MIKROBUS( mikrobus, MIKROBUS_PWM );    \
    cfg.int_pin = MIKROBUS( mikrobus, MIKROBUS_INT )
 
 // nvsram4_map
 // nvsram4
 
typedef struct
{
    // Output pins
 
     digital_out_t  hld;       
     digital_out_t  hsb;       
     digital_out_t  wp;        
    // Input pins
 
     digital_in_t  int_pin;    
    // Modules
 
    spi_master_t  spi;         
    pin_name_t  chip_select;   
} nvsram4_t;
 
typedef struct
{
    // Communication gpio pins
 
    pin_name_t  miso;       
    pin_name_t  mosi;       
    pin_name_t  sck;        
    pin_name_t  cs;         
    // Additional gpio pins
 
     pin_name_t  hld;       
     pin_name_t  hsb;       
     pin_name_t  wp;        
     pin_name_t  int_pin;   
    // static variable
 
    uint32_t                           spi_speed;        
    spi_master_mode_t                  spi_mode;         
    spi_master_chip_select_polarity_t  cs_polarity;      
} nvsram4_cfg_t;
 
typedef struct 
{
    
    uint8_t hours; 
    uint8_t min;
    uint8_t sec; 
    
} nvsram4_rtc_time_t;
 
typedef struct 
{
    
    uint8_t year;
    uint8_t month;
    uint8_t day;
    uint8_t day_of_week;
    
 
} nvsram4_rtc_date_t;
 
typedef struct 
{
    
    uint8_t day;
    uint8_t hours; 
    uint8_t min;
    uint8_t sec; 
    
} nvsram4_rtc_alarm_t;
 
void nvsram4_cfg_setup ( nvsram4_cfg_t *cfg );
 
err_t nvsram4_init ( nvsram4_t *ctx, nvsram4_cfg_t *cfg );
 
void nvsram4_default_cfg ( nvsram4_t *ctx );
 
err_t nvsram4_generic_write ( nvsram4_t *ctx, uint8_t reg, uint8_t *data_in, uint8_t len );
 
err_t nvsram4_generic_read ( nvsram4_t *ctx, uint8_t reg, uint8_t *data_out, uint8_t len );
 
err_t nvsram4_set_cmd ( nvsram4_t *ctx, uint8_t cmd );
 
uint8_t nvsram4_read_status ( nvsram4_t *ctx );
 
void nvsram4_write_status ( nvsram4_t *ctx, uint8_t st_data );
 
err_t nvsram4_burst_read_memory ( nvsram4_t *ctx, uint32_t mem_addr, uint8_t *data_out, uint8_t n_bytes );
 
err_t nvsram4_burst_write_memory ( nvsram4_t *ctx, uint32_t mem_addr, uint8_t *data_in, uint8_t n_bytes );
 
uint32_t nvsram4_read_id ( nvsram4_t *ctx );
 
uint8_t nvsram4_rtc_read_reg ( nvsram4_t *ctx, uint8_t rtc_reg );
 
void nvsram4_rtc_write_reg ( nvsram4_t *ctx, uint8_t rtc_reg, uint8_t data_in );
 
void nvsram4_enable_rtc_write ( nvsram4_t *ctx );
 
void nvsram4_disable_rtc_write ( nvsram4_t *ctx );
 
void nvsram4_get_rtc_time ( nvsram4_t *ctx, nvsram4_rtc_time_t *rtc_time );
 
err_t nvsram4_set_rtc_time ( nvsram4_t *ctx, nvsram4_rtc_time_t rtc_time );
 
void nvsram4_get_rtc_date ( nvsram4_t *ctx, nvsram4_rtc_date_t *rtc_date );
 
err_t nvsram4_set_rtc_date ( nvsram4_t *ctx, nvsram4_rtc_date_t rtc_date );
 
void nvsram4_get_rtc_alarm ( nvsram4_t *ctx, nvsram4_rtc_alarm_t *rtc_alarm );
 
err_t nvsram4_set_rtc_alarm ( nvsram4_t *ctx, nvsram4_rtc_alarm_t rtc_alarm );
 
err_t nvsram4_hold ( nvsram4_t *ctx, uint8_t en_hold );
 
err_t nvsram4_hardware_store ( nvsram4_t *ctx, uint8_t en_hw_store );
 
err_t nvsram4_hw_write_protection ( nvsram4_t *ctx, uint8_t en_wp );
 
#ifdef __cplusplus
}
#endif
#endif // NVSRAM4_H
 
 // nvsram4
 
// ------------------------------------------------------------------------ END