Device Control Reg

Macros
#define	PIXI_CTL_ADCCTL_IDLE   0x0000
#define	PIXI_CTL_ADCCTL_SINGLESWEEP   0x0001
#define	PIXI_CTL_ADCCTL_SINGLECONV   0x0002
#define	PIXI_CTL_ADCCTL_CONTSWEEP   0x0003
#define	PIXI_CTL_DACCTL_SEQUPDATE   0x0000
#define	PIXI_CTL_DACCTL_IMMUPDATE   0x0001 << 2
#define	PIXI_CTL_DACCTL_USEPRST_1   0x0002 << 2
#define	PIXI_CTL_DACCTL_USEPRST_2   0x0003 << 2
#define	PIXI_CTL_ADCCONV_200KSPS   0x0000
#define	PIXI_CTL_ADCCONV_250KSPS   0x0001 << 4
#define	PIXI_CTL_ADCCONV_333KSPS   0x0002 << 4
#define	PIXI_CTL_ADCCONV_400KSPS   0x0003 << 4
#define	PIXI_CTL_DACREF_INTREF   0x0001 << 6
#define	PIXI_CTL_THSHDN_ENABLE   0x0001 << 7
#define	PIXI_CTL_TMPCTL_INT   0x0001 << 8
#define	PIXI_CTL_TMPCTL_EXT_1   0x0002 << 8
#define	PIXI_CTL_TMPCTL_EXT_2   0x0004 << 8
#define	PIXI_CTL_TMPPER_EXTENDED   0x0001 << 11
#define	PIXI_CTL_RS_CANCEL_ENABLE   0x0001 << 12
#define	PIXI_CTL_LPEN_LOWPOWER   0x0001 << 13
#define	PIXI_CTL_BRST_CONTEX_INC   0x0001 << 14
#define	PIXI_CTL_RESET   0x0001 << 15

Detailed Description

Macro Definition Documentation

PIXI_CTL_ADCCONV_200KSPS

#define PIXI_CTL_ADCCONV_200KSPS   0x0000

PIXI_CTL_ADCCONV_250KSPS

#define PIXI_CTL_ADCCONV_250KSPS   0x0001 << 4

PIXI_CTL_ADCCONV_333KSPS

#define PIXI_CTL_ADCCONV_333KSPS   0x0002 << 4

PIXI_CTL_ADCCONV_400KSPS

#define PIXI_CTL_ADCCONV_400KSPS   0x0003 << 4

PIXI_CTL_ADCCTL_CONTSWEEP

#define PIXI_CTL_ADCCTL_CONTSWEEP   0x0003

PIXI_CTL_ADCCTL_IDLE

#define PIXI_CTL_ADCCTL_IDLE   0x0000

PIXI_CTL_ADCCTL_SINGLECONV

#define PIXI_CTL_ADCCTL_SINGLECONV   0x0002

PIXI_CTL_ADCCTL_SINGLESWEEP

#define PIXI_CTL_ADCCTL_SINGLESWEEP   0x0001

PIXI_CTL_BRST_CONTEX_INC

#define PIXI_CTL_BRST_CONTEX_INC   0x0001 << 14

PIXI_CTL_DACCTL_IMMUPDATE

#define PIXI_CTL_DACCTL_IMMUPDATE   0x0001 << 2

PIXI_CTL_DACCTL_SEQUPDATE

#define PIXI_CTL_DACCTL_SEQUPDATE   0x0000

PIXI_CTL_DACCTL_USEPRST_1

#define PIXI_CTL_DACCTL_USEPRST_1   0x0002 << 2

PIXI_CTL_DACCTL_USEPRST_2

#define PIXI_CTL_DACCTL_USEPRST_2   0x0003 << 2

PIXI_CTL_DACREF_INTREF

#define PIXI_CTL_DACREF_INTREF   0x0001 << 6

PIXI_CTL_LPEN_LOWPOWER

#define PIXI_CTL_LPEN_LOWPOWER   0x0001 << 13

PIXI_CTL_RESET

#define PIXI_CTL_RESET   0x0001 << 15

PIXI_CTL_RS_CANCEL_ENABLE

#define PIXI_CTL_RS_CANCEL_ENABLE   0x0001 << 12

PIXI_CTL_THSHDN_ENABLE

#define PIXI_CTL_THSHDN_ENABLE   0x0001 << 7

PIXI_CTL_TMPCTL_EXT_1

#define PIXI_CTL_TMPCTL_EXT_1   0x0002 << 8

PIXI_CTL_TMPCTL_EXT_2

#define PIXI_CTL_TMPCTL_EXT_2   0x0004 << 8

PIXI_CTL_TMPCTL_INT

#define PIXI_CTL_TMPCTL_INT   0x0001 << 8

PIXI_CTL_TMPPER_EXTENDED

#define PIXI_CTL_TMPPER_EXTENDED   0x0001 << 11