Macros
#define	PIXI_REG_GPO_DATA 0x0D

#define	PIXI_REG_DEVICE_CONTROL 0x10

#define	PIXI_REG_INTERRUPT_MASK 0x11

#define	PIXI_REG_GPI_IRQMODE 0x12

#define	PIXI_REG_DAC_PRESET_1 0x16

#define	PIXI_REG_DAC_PRESET_2 0x17

#define	PIXI_REG_TEMP_MONITOR_CONFIG 0x18

#define	PIXI_REG_TEMP_IN_THRES_HIGH 0x19

#define	PIXI_REG_TEMP_IN_THRES_LOW 0x1A

#define	PIXI_REG_TEMP_EXT_1_THRES_HIGH 0x1B

#define	PIXI_REG_TEMP_EXT_1_THRES_LOW 0x1C

#define	PIXI_REG_TEMP_EXT_2_THRES_HIGH 0x1D

#define	PIXI_REG_TEMP_EXT_2_THRES_LOW 0x1E

#define	PIXI_REG_PORT_CONFIG_BASE 0x20

#define	PIXI_REG_DAC_DATA_BASE 0x60

Detailed Description

Macro Definition Documentation

◆ PIXI_REG_DAC_DATA_BASE

#define PIXI_REG_DAC_DATA_BASE 0x60

◆ PIXI_REG_DAC_PRESET_1

#define PIXI_REG_DAC_PRESET_1 0x16

◆ PIXI_REG_DAC_PRESET_2

#define PIXI_REG_DAC_PRESET_2 0x17

◆ PIXI_REG_DEVICE_CONTROL

#define PIXI_REG_DEVICE_CONTROL 0x10

◆ PIXI_REG_GPI_IRQMODE

#define PIXI_REG_GPI_IRQMODE 0x12

◆ PIXI_REG_GPO_DATA

#define PIXI_REG_GPO_DATA 0x0D

◆ PIXI_REG_INTERRUPT_MASK

#define PIXI_REG_INTERRUPT_MASK 0x11

◆ PIXI_REG_PORT_CONFIG_BASE

#define PIXI_REG_PORT_CONFIG_BASE 0x20

◆ PIXI_REG_TEMP_EXT_1_THRES_HIGH

#define PIXI_REG_TEMP_EXT_1_THRES_HIGH 0x1B

◆ PIXI_REG_TEMP_EXT_1_THRES_LOW

#define PIXI_REG_TEMP_EXT_1_THRES_LOW 0x1C

◆ PIXI_REG_TEMP_EXT_2_THRES_HIGH

#define PIXI_REG_TEMP_EXT_2_THRES_HIGH 0x1D

◆ PIXI_REG_TEMP_EXT_2_THRES_LOW

#define PIXI_REG_TEMP_EXT_2_THRES_LOW 0x1E

◆ PIXI_REG_TEMP_IN_THRES_HIGH

#define PIXI_REG_TEMP_IN_THRES_HIGH 0x19

◆ PIXI_REG_TEMP_IN_THRES_LOW

#define PIXI_REG_TEMP_IN_THRES_LOW 0x1A

◆ PIXI_REG_TEMP_MONITOR_CONFIG

#define PIXI_REG_TEMP_MONITOR_CONFIG 0x18

Macros