pressure3 2.0.0.0
Macros
Interrupt and FIFO configuration
Pressure 3 Click Driver » Macros

Macros

#define PRESSURE3_BIT_MASK_CFG_REG_INT_HL_LOW   0x00
 
#define PRESSURE3_BIT_MASK_CFG_REG_INT_HL_HIGH   0x80
 
#define PRESSURE3_BIT_MASK_CFG_REG_INT_FIFO_DISABLE   0x00
 
#define PRESSURE3_BIT_MASK_CFG_REG_INT_FIFO_ENABLE   0x40
 
#define PRESSURE3_BIT_MASK_CFG_REG_INT_TMP_DISABLE   0x00
 
#define PRESSURE3_BIT_MASK_CFG_REG_INT_TMP_ENABLE   0x20
 
#define PRESSURE3_BIT_MASK_CFG_REG_INT_PRS_DISABLE   0x00
 
#define PRESSURE3_BIT_MASK_CFG_REG_INT_PRS_ENABLE   0x10
 
#define PRESSURE3_BIT_MASK_CFG_REG_T_SHIFT_NO_SHIFT   0x00
 
#define PRESSURE3_BIT_MASK_CFG_REG_T_SHIFT_SHIFT   0x08
 
#define PRESSURE3_BIT_MASK_CFG_REG_P_SHIFT_NO_SHIFT   0x00
 
#define PRESSURE3_BIT_MASK_CFG_REG_P_SHIFT_SHIFT   0x04
 
#define PRESSURE3_BIT_MASK_CFG_REG_FIFO_EN_DISABLE   0x00
 
#define PRESSURE3_BIT_MASK_CFG_REG_FIFO_EN_ENABLE   0x02
 
#define PRESSURE3_BIT_MASK_CFG_REG_SPI_MODE_DISABLE   0x00
 
#define PRESSURE3_BIT_MASK_CFG_REG_SPI_MODE_ENABLE   0x01
 

Detailed Description

Macro Definition Documentation

◆ PRESSURE3_BIT_MASK_CFG_REG_FIFO_EN_DISABLE

#define PRESSURE3_BIT_MASK_CFG_REG_FIFO_EN_DISABLE   0x00

◆ PRESSURE3_BIT_MASK_CFG_REG_FIFO_EN_ENABLE

#define PRESSURE3_BIT_MASK_CFG_REG_FIFO_EN_ENABLE   0x02

◆ PRESSURE3_BIT_MASK_CFG_REG_INT_FIFO_DISABLE

#define PRESSURE3_BIT_MASK_CFG_REG_INT_FIFO_DISABLE   0x00

◆ PRESSURE3_BIT_MASK_CFG_REG_INT_FIFO_ENABLE

#define PRESSURE3_BIT_MASK_CFG_REG_INT_FIFO_ENABLE   0x40

◆ PRESSURE3_BIT_MASK_CFG_REG_INT_HL_HIGH

#define PRESSURE3_BIT_MASK_CFG_REG_INT_HL_HIGH   0x80

◆ PRESSURE3_BIT_MASK_CFG_REG_INT_HL_LOW

#define PRESSURE3_BIT_MASK_CFG_REG_INT_HL_LOW   0x00

◆ PRESSURE3_BIT_MASK_CFG_REG_INT_PRS_DISABLE

#define PRESSURE3_BIT_MASK_CFG_REG_INT_PRS_DISABLE   0x00

◆ PRESSURE3_BIT_MASK_CFG_REG_INT_PRS_ENABLE

#define PRESSURE3_BIT_MASK_CFG_REG_INT_PRS_ENABLE   0x10

◆ PRESSURE3_BIT_MASK_CFG_REG_INT_TMP_DISABLE

#define PRESSURE3_BIT_MASK_CFG_REG_INT_TMP_DISABLE   0x00

◆ PRESSURE3_BIT_MASK_CFG_REG_INT_TMP_ENABLE

#define PRESSURE3_BIT_MASK_CFG_REG_INT_TMP_ENABLE   0x20

◆ PRESSURE3_BIT_MASK_CFG_REG_P_SHIFT_NO_SHIFT

#define PRESSURE3_BIT_MASK_CFG_REG_P_SHIFT_NO_SHIFT   0x00

◆ PRESSURE3_BIT_MASK_CFG_REG_P_SHIFT_SHIFT

#define PRESSURE3_BIT_MASK_CFG_REG_P_SHIFT_SHIFT   0x04

◆ PRESSURE3_BIT_MASK_CFG_REG_SPI_MODE_DISABLE

#define PRESSURE3_BIT_MASK_CFG_REG_SPI_MODE_DISABLE   0x00

◆ PRESSURE3_BIT_MASK_CFG_REG_SPI_MODE_ENABLE

#define PRESSURE3_BIT_MASK_CFG_REG_SPI_MODE_ENABLE   0x01

◆ PRESSURE3_BIT_MASK_CFG_REG_T_SHIFT_NO_SHIFT

#define PRESSURE3_BIT_MASK_CFG_REG_T_SHIFT_NO_SHIFT   0x00

◆ PRESSURE3_BIT_MASK_CFG_REG_T_SHIFT_SHIFT

#define PRESSURE3_BIT_MASK_CFG_REG_T_SHIFT_SHIFT   0x08