Macros
#define	RTC7_CONFIG1_REG 0x00

#define	RTC7_CONFIG2_REG 0x01

#define	RTC7_SLEEP_CONFIG_REG 0x02

#define	RTC7_TIMER_CONFIG_REG 0x03

#define	RTC7_INT_EN_REG 0x04

#define	RTC7_INT_STATUS_REG 0x05

#define	RTC7_ALM1_SEC_REG 0x0D

#define	RTC7_ALM1_MIN_REG 0x0E

#define	RTC7_ALM1_HRS_REG 0x0F

#define	RTC7_ALM1_DAY_DATE_REG 0x10

#define	RTC7_ALM2_MIN_REG 0x11

#define	RTC7_ALM2_HRS_REG 0x12

#define	RTC7_ALM2_DAY_DATE_REG 0x13

#define	RTC7_TIMER_COUNT_REG 0x14

#define	RTC7_TIMER_INIT_REG 0x15

#define	RTC7_RAM0_REG_ADDR16H 0x16

#define	RTC7_RAM63_REG_ADDR55H 0x55

#define	RTC7_PWR_MGMT_REG 0x56

#define	RTC7_TRICKLE_REG 0x57

#define	RTC7_SPARE_REG 0x58

#define	RTC7_SPARE_ST_REG 0x59

#define	RTC7_TEST1_REG 0x64

#define	RTC7_TEST2_REG 0x65

#define	RTC7_TEST3_REG 0x66

#define	RTC7_TCFG1_REG 0x67

#define	RTC7_TCFG2_REG 0x68

#define	RTC7_TCFG3_REG 0x69

#define	RTC7_OTP1_B1_REG 0x6A

#define	RTC7_OTP1_B2_REG 0x6B

#define	RTC7_OTP1_B3_REG 0x6C

#define	RTC7_OTP1_B4_REG 0x6D

#define	RTC7_OTP2_B1_REG 0x6E

#define	RTC7_OTP2_B2_REG 0x6F

#define	RTC7_OTP2_B3_REG 0x70

#define	RTC7_OTP2_B4_REG 0x71

#define	RTC7_TCFG4_REG 0x72

#define	RTC7_TCFG5_REG 0x73

#define	RTC7_TEST_DIG_REG 0x74

Detailed Description

Macro Definition Documentation

◆ RTC7_ALM1_DAY_DATE_REG

#define RTC7_ALM1_DAY_DATE_REG 0x10

◆ RTC7_ALM1_HRS_REG

#define RTC7_ALM1_HRS_REG 0x0F

◆ RTC7_ALM1_MIN_REG

#define RTC7_ALM1_MIN_REG 0x0E

◆ RTC7_ALM1_SEC_REG

#define RTC7_ALM1_SEC_REG 0x0D

◆ RTC7_ALM2_DAY_DATE_REG

#define RTC7_ALM2_DAY_DATE_REG 0x13

◆ RTC7_ALM2_HRS_REG

#define RTC7_ALM2_HRS_REG 0x12

◆ RTC7_ALM2_MIN_REG

#define RTC7_ALM2_MIN_REG 0x11

◆ RTC7_CONFIG1_REG

#define RTC7_CONFIG1_REG 0x00

◆ RTC7_CONFIG2_REG

#define RTC7_CONFIG2_REG 0x01

◆ RTC7_INT_EN_REG

#define RTC7_INT_EN_REG 0x04

◆ RTC7_INT_STATUS_REG

#define RTC7_INT_STATUS_REG 0x05

◆ RTC7_OTP1_B1_REG

#define RTC7_OTP1_B1_REG 0x6A

◆ RTC7_OTP1_B2_REG

#define RTC7_OTP1_B2_REG 0x6B

◆ RTC7_OTP1_B3_REG

#define RTC7_OTP1_B3_REG 0x6C

◆ RTC7_OTP1_B4_REG

#define RTC7_OTP1_B4_REG 0x6D

◆ RTC7_OTP2_B1_REG

#define RTC7_OTP2_B1_REG 0x6E

◆ RTC7_OTP2_B2_REG

#define RTC7_OTP2_B2_REG 0x6F

◆ RTC7_OTP2_B3_REG

#define RTC7_OTP2_B3_REG 0x70

◆ RTC7_OTP2_B4_REG

#define RTC7_OTP2_B4_REG 0x71

◆ RTC7_PWR_MGMT_REG

#define RTC7_PWR_MGMT_REG 0x56

◆ RTC7_RAM0_REG_ADDR16H

#define RTC7_RAM0_REG_ADDR16H 0x16

◆ RTC7_RAM63_REG_ADDR55H

#define RTC7_RAM63_REG_ADDR55H 0x55

◆ RTC7_SLEEP_CONFIG_REG

#define RTC7_SLEEP_CONFIG_REG 0x02

◆ RTC7_SPARE_REG

#define RTC7_SPARE_REG 0x58

◆ RTC7_SPARE_ST_REG

#define RTC7_SPARE_ST_REG 0x59

◆ RTC7_TCFG1_REG

#define RTC7_TCFG1_REG 0x67

◆ RTC7_TCFG2_REG

#define RTC7_TCFG2_REG 0x68

◆ RTC7_TCFG3_REG

#define RTC7_TCFG3_REG 0x69

◆ RTC7_TCFG4_REG

#define RTC7_TCFG4_REG 0x72

◆ RTC7_TCFG5_REG

#define RTC7_TCFG5_REG 0x73

◆ RTC7_TEST1_REG

#define RTC7_TEST1_REG 0x64

◆ RTC7_TEST2_REG

#define RTC7_TEST2_REG 0x65

◆ RTC7_TEST3_REG

#define RTC7_TEST3_REG 0x66

◆ RTC7_TEST_DIG_REG

#define RTC7_TEST_DIG_REG 0x74

◆ RTC7_TIMER_CONFIG_REG

#define RTC7_TIMER_CONFIG_REG 0x03

◆ RTC7_TIMER_COUNT_REG

#define RTC7_TIMER_COUNT_REG 0x14

◆ RTC7_TIMER_INIT_REG

#define RTC7_TIMER_INIT_REG 0x15

◆ RTC7_TRICKLE_REG

#define RTC7_TRICKLE_REG 0x57

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