Macros
#define	RTD2_REG_MUX0 0x00

#define	RTD2_REG_VBIAS 0x01

#define	RTD2_REG_MUX1 0x02

#define	RTD2_REG_SYS0 0x03

#define	RTD2_REG_OFC0 0x04

#define	RTD2_REG_OFC1 0x05

#define	RTD2_REG_OFC2 0x06

#define	RTD2_REG_FSC0 0x07

#define	RTD2_REG_FSC1 0x08

#define	RTD2_REG_FSC2 0x09

#define	RTD2_REG_IDAC0 0x0A

#define	RTD2_REG_IDAC1 0x0B

#define	RTD2_REG_GPIOCFG 0x0C

#define	RTD2_REG_GPIODIR 0x0D

#define	RTD2_REG_GPIODAT 0x0E

Detailed Description

Macro Definition Documentation

◆ RTD2_REG_FSC0

#define RTD2_REG_FSC0 0x07

◆ RTD2_REG_FSC1

#define RTD2_REG_FSC1 0x08

◆ RTD2_REG_FSC2

#define RTD2_REG_FSC2 0x09

◆ RTD2_REG_GPIOCFG

#define RTD2_REG_GPIOCFG 0x0C

◆ RTD2_REG_GPIODAT

#define RTD2_REG_GPIODAT 0x0E

◆ RTD2_REG_GPIODIR

#define RTD2_REG_GPIODIR 0x0D

◆ RTD2_REG_IDAC0

#define RTD2_REG_IDAC0 0x0A

◆ RTD2_REG_IDAC1

#define RTD2_REG_IDAC1 0x0B

◆ RTD2_REG_MUX0

#define RTD2_REG_MUX0 0x00

◆ RTD2_REG_MUX1

#define RTD2_REG_MUX1 0x02

◆ RTD2_REG_OFC0

#define RTD2_REG_OFC0 0x04

◆ RTD2_REG_OFC1

#define RTD2_REG_OFC1 0x05

◆ RTD2_REG_OFC2

#define RTD2_REG_OFC2 0x06

◆ RTD2_REG_SYS0

#define RTD2_REG_SYS0 0x03

◆ RTD2_REG_VBIAS

#define RTD2_REG_VBIAS 0x01

Macros