spiextend.h

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/****************************************************************************
** Copyright (C) 2020 MikroElektronika d.o.o.
** Contact: https://www.mikroe.com/contact
**
** Permission is hereby granted, free of charge, to any person obtaining a copy
** of this software and associated documentation files (the "Software"), to deal
** in the Software without restriction, including without limitation the rights
** to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
** copies of the Software, and to permit persons to whom the Software is
** furnished to do so, subject to the following conditions:
** The above copyright notice and this permission notice shall be
** included in all copies or substantial portions of the Software.
**
** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
**  USE OR OTHER DEALINGS IN THE SOFTWARE.
****************************************************************************/
 
#ifndef SPIEXTEND_H
#define SPIEXTEND_H
 
#ifdef __cplusplus
extern "C"{
#endif
 
#ifdef PREINIT_SUPPORTED
#include "preinit.h"
#endif
 
#ifdef MikroCCoreVersion
    #if MikroCCoreVersion >= 1
        #include "delays.h"
    #endif
#endif
 
#include "drv_digital_out.h"
#include "drv_digital_in.h"
#include "drv_spi_master.h"
#include "spi_specifics.h"
 
#define SPIEXTEND_REG_CONFIG                                     0x00
#define SPIEXTEND_REG_STATUS                                     0x01
#define SPIEXTEND_REG_EVENT                                      0x02
#define SPIEXTEND_REG_INT_EN                                     0x03
#define SPIEXTEND_REG_FAULT                                      0x04
#define SPIEXTEND_REG_WORD_LENGTH                                0x05
#define SPIEXTEND_REG_SCRATCH                                    0x06
 
#define SPIEXTEND_ACCEL14_REG_WHO_AM_I                           0x0F
#define SPIEXTEND_ACCEL14_REG_CTRL1_XL                           0x10
#define SPIEXTEND_ACCEL14_REG_CTRL3_C                            0x12
#define SPIEXTEND_ACCEL14_REG_OUT_TEMP_L                         0x20
#define SPIEXTEND_ACCEL14_REG_OUT_TEMP_H                         0x21
#define SPIEXTEND_ACCEL14_REG_OUTX_L_A                           0x28
#define SPIEXTEND_ACCEL14_REG_OUTX_H_A                           0x29
#define SPIEXTEND_ACCEL14_REG_OUTY_L_A                           0x2A
#define SPIEXTEND_ACCEL14_REG_OUTY_H_A                           0x2B
#define SPIEXTEND_ACCEL14_REG_OUTZ_L_A                           0x2C
#define SPIEXTEND_ACCEL14_REG_OUTZ_H_A                           0x2D
 // spiextend_reg
 
#define SPIEXTEND_STATUS_ACTIVE                                  0x00
#define SPIEXTEND_STATUS_INACTIVE                                0x01
 
#define SPIEXTEND_ACCEL14_CTRL1_XL_POWER_UP                      0xA0
#define SPIEXTEND_ACCEL14_CTRL1_XL_HIGH_RES_FS                   0x00
#define SPIEXTEND_ACCEL14_CTRL1_XL_GSEL_4G                       0x08
#define SPIEXTEND_ACCEL14_CTRL3_C_BOOT_NORMAL                    0x00
#define SPIEXTEND_ACCEL14_CTRL3_C_BDU_READ_UPDATE                0x40
#define SPIEXTEND_ACCEL14_CTRL3_C_INT_ACTIVE_HIGH                0x00
#define SPIEXTEND_ACCEL14_CTRL3_C_PP_OD_PUSH_PULL                0x00
#define SPIEXTEND_ACCEL14_CTRL3_C_SIM_SPI_4_WIRE                 0x00
#define SPIEXTEND_ACCEL14_CTRL3_C_IF_INC_ENABLE                  0x04
#define SPIEXTEND_ACCEL14_CTRL3_C_SW_RESET_DIS                   0x00
 
#define SPIEXTEND_ACCEL14_SPI_WRITE                              0x00
#define SPIEXTEND_ACCEL14_SPI_READ                               0x80
 
#define SPIEXTEND_CMD_CLEAR_EVENT                                0x00
 
#define SPIEXTEND_SLAVE_SELECT_SS1                               0x01
#define SPIEXTEND_SLAVE_SELECT_SS2                               0x02
#define SPIEXTEND_SLAVE_SELECT_SS3                               0x03
 
#define SPIEXTEND_PIN_STATE_LOW                                  0x00
#define SPIEXTEND_PIN_STATE_HIGH                                 0x01
 
#define SPIEXTEND_SPI_WRITE                                      0x00
#define SPIEXTEND_SPI_READ                                       0x01
 
#define SPIEXTEND_SET_DATA_SAMPLE_EDGE      SET_SPI_DATA_SAMPLE_EDGE
#define SPIEXTEND_SET_DATA_SAMPLE_MIDDLE    SET_SPI_DATA_SAMPLE_MIDDLE
 
 // spiextend_set
 
#define SPIEXTEND_MAP_MIKROBUS( cfg, mikrobus ) \
    cfg.miso = MIKROBUS( mikrobus, MIKROBUS_MISO ); \
    cfg.mosi = MIKROBUS( mikrobus, MIKROBUS_MOSI ); \
    cfg.sck  = MIKROBUS( mikrobus, MIKROBUS_SCK ); \
    cfg.cs   = MIKROBUS( mikrobus, MIKROBUS_CS ); \
    cfg.ss3 = MIKROBUS( mikrobus, MIKROBUS_AN ); \
    cfg.ss2 = MIKROBUS( mikrobus, MIKROBUS_RST ); \
    cfg.ssc = MIKROBUS( mikrobus, MIKROBUS_PWM ); \
    cfg.int_pin = MIKROBUS( mikrobus, MIKROBUS_INT )
 
 // spiextend_map
 // spiextend
 
typedef struct
{
    // Output pins
    digital_out_t  ss3;        
    digital_out_t  ss2;        
    digital_out_t  ssc;        
    // Input pins
    digital_in_t  int_pin;     
    // Modules
    spi_master_t  spi;                               
    pin_name_t  chip_select;                         
} spiextend_t;
 
typedef struct
{
    // Communication gpio pins
    pin_name_t  miso;                                    
    pin_name_t  mosi;                                    
    pin_name_t  sck;                                     
    pin_name_t  cs;                                      
    // Additional gpio pins
    pin_name_t   ss3;           
    pin_name_t  ss2;            
    pin_name_t  ssc;            
    pin_name_t  int_pin;        
    // static variable
    uint32_t                           spi_speed;        
    spi_master_mode_t                  spi_mode;         
    spi_master_chip_select_polarity_t  cs_polarity;      
} spiextend_cfg_t;
 
typedef struct
{
    uint8_t rem_ss3_pol;
    uint8_t rem_ss3_pha;
    uint8_t rem_ss2_pol;
    uint8_t rem_ss2_pha;
    uint8_t rem_ss1_pol;
    uint8_t rem_ss1_pha;
}
spiextend_config_data_t;
 
typedef struct
{
    uint8_t nlink;
    uint8_t nint;
    uint8_t rmt_nint;
    uint8_t speed_idx;
}
spiextend_status_data_t;
 
typedef struct
{
    uint8_t e_link_good;
    uint8_t e_link_lost;
    uint8_t e_fault;
}
spiextend_event_data_t;
 
typedef struct
{
    uint8_t spi_write_fault;
    uint8_t link_fault;
    uint8_t rmt_spi_fault;
    uint8_t tx_buf_overflow;
    uint8_t tx_buf_underflow;
}
spiextend_fault_data_t;
 
typedef enum
{
   SPIEXTEND_OK = 0,
   SPIEXTEND_ERROR = -1
 
} spiextend_return_value_t;
 
void spiextend_cfg_setup ( spiextend_cfg_t *cfg );
 
err_t spiextend_init ( spiextend_t *ctx, spiextend_cfg_t *cfg );
 
err_t spiextend_default_cfg ( spiextend_t *ctx );
 
err_t spiextend_generic_write ( spiextend_t *ctx, uint8_t reg, uint8_t data_in );
 
err_t spiextend_generic_read ( spiextend_t *ctx, uint8_t reg, uint8_t *data_out );
 
void spiextend_get_config ( spiextend_t *ctx, spiextend_config_data_t *config_data );
 
void spiextend_set_config ( spiextend_t *ctx, spiextend_config_data_t config_data );
 
void spiextend_get_status ( spiextend_t *ctx, spiextend_status_data_t *status_data );
 
void spiextend_get_event ( spiextend_t *ctx, spiextend_event_data_t *event_data );
 
void spiextend_clear_event ( spiextend_t *ctx );
 
void spiextend_enable_int ( spiextend_t *ctx, spiextend_event_data_t event_data );
 
void spiextend_get_fault ( spiextend_t *ctx, spiextend_fault_data_t *fault_data );
 
uint8_t spiextend_get_word_length ( spiextend_t *ctx );
 
void spiextend_set_word_length ( spiextend_t *ctx, uint8_t word_length );
 
uint8_t spiextend_get_scratch (  spiextend_t *ctx );
 
void spiextend_set_scratch ( spiextend_t *ctx, uint8_t scratch );
 
void spiextend_set_ss1 ( spiextend_t *ctx, uint8_t en_cs );
 
void spiextend_set_ss2 ( spiextend_t *ctx, uint8_t en_rst );
 
void spiextend_set_ss3 ( spiextend_t *ctx, uint8_t en_an );
 
uint8_t spiextend_check_int ( spiextend_t *ctx );
 
void spiextend_rmt_spi_write ( spiextend_t *ctx, uint8_t *p_tx_data, uint16_t n_bytes );
 
void spiextend_rmt_spi_read ( spiextend_t *ctx, uint8_t *p_rx_data, uint16_t n_bytes );
 
void spiextend_rmt_write ( spiextend_t *ctx, uint8_t reg, uint8_t tx_data, uint8_t sel_slave );
 
uint8_t spiextend_rmt_read ( spiextend_t *ctx, uint8_t reg, uint8_t sel_slave );
 
void spiextend_rmt_multi_write ( spiextend_t *ctx, uint8_t reg, uint8_t *p_tx_data, uint16_t n_bytes, uint8_t sel_slave );
 
void spiextend_rmt_multi_read ( spiextend_t *ctx, uint8_t reg, uint8_t *p_rx_data, uint8_t n_bytes, uint8_t sel_slave );
 
#ifdef __cplusplus
}
#endif
#endif // SPIEXTEND_H
 
 // spiextend
 
// ------------------------------------------------------------------------ END