sram3.h

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/****************************************************************************
** Copyright (C) 2020 MikroElektronika d.o.o.
** Contact: https://www.mikroe.com/contact
**
** Permission is hereby granted, free of charge, to any person obtaining a copy
** of this software and associated documentation files (the "Software"), to deal
** in the Software without restriction, including without limitation the rights
** to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
** copies of the Software, and to permit persons to whom the Software is
** furnished to do so, subject to the following conditions:
** The above copyright notice and this permission notice shall be
** included in all copies or substantial portions of the Software.
**
** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
**  USE OR OTHER DEALINGS IN THE SOFTWARE.
****************************************************************************/
 
#ifndef SRAM3_H
#define SRAM3_H
 
#ifdef __cplusplus
extern "C"{
#endif
 
#ifdef PREINIT_SUPPORTED
#include "preinit.h"
#endif
 
#ifdef MikroCCoreVersion
    #if MikroCCoreVersion >= 1
        #include "delays.h"
    #endif
#endif
 
#include "drv_digital_out.h"
#include "drv_digital_in.h"
#include "drv_spi_master.h"
 
#define SRAM3_OPCODE_WREN                   0x06
#define SRAM3_OPCODE_WRDI                   0x04
#define SRAM3_OPCODE_RDSR                   0x05
#define SRAM3_OPCODE_WRSR                   0x01
#define SRAM3_OPCODE_READ                   0x03
#define SRAM3_OPCODE_SECURE_READ            0x13
#define SRAM3_OPCODE_WRITE                  0x02
#define SRAM3_OPCODE_SECURE_WRITE           0x12
#define SRAM3_OPCODE_STORE                  0x08
#define SRAM3_OPCODE_RECALL                 0x09
#define SRAM3_OPCODE_WRSNR                  0xC2
#define SRAM3_OPCODE_RDSNR                  0xC3
#define SRAM3_OPCODE_HIBERNATE              0xB9
 
#define SRAM3_PROT_NONE                     0x00
#define SRAM3_PROT_QUART                    0x04
#define SRAM3_PROT_HALF                     0x08
#define SRAM3_PROT_ALL                      0x0C
                                    
#define SRAM3_STATS_RDY_BIT                 0x01
#define SRAM3_STATS_WEN_BIT                 0x02
#define SRAM3_STATS_SWM_BIT                 0x10
#define SRAM3_STATS_PDIS_BIT                0x40
 
#define SRAM3_SERIAL_LEN                    0x10
#define SRAM3_SECURE_BUF_SIZE               0x80
 // sram3_set
 
#define SRAM3_MAP_MIKROBUS( cfg, mikrobus ) \
    cfg.miso = MIKROBUS( mikrobus, MIKROBUS_MISO ); \
    cfg.mosi = MIKROBUS( mikrobus, MIKROBUS_MOSI ); \
    cfg.sck  = MIKROBUS( mikrobus, MIKROBUS_SCK ); \
    cfg.cs   = MIKROBUS( mikrobus, MIKROBUS_CS ); \
    cfg.hold = MIKROBUS( mikrobus, MIKROBUS_PWM ) 
 
 // sram3_map
 // sram3
 
typedef struct
{
    // Output pins
    digital_out_t  hold;            
    // Modules
    spi_master_t  spi;              
    pin_name_t  chip_select;        
} sram3_t;
 
typedef struct
{
    // Communication gpio pins
    pin_name_t  miso;               
    pin_name_t  mosi;               
    pin_name_t  sck;                
    pin_name_t  cs;                 
    // Additional gpio pins    
    pin_name_t  hold;               
    // static variable    
    uint32_t                           spi_speed;        
    spi_master_mode_t                  spi_mode;         
    spi_master_chip_select_polarity_t  cs_polarity;      
} sram3_cfg_t;
 
typedef enum
{
   SRAM3_OK = 0,
   SRAM3_ERROR = -1
 
} sram3_return_value_t;
 
void sram3_cfg_setup ( sram3_cfg_t *cfg );
 
err_t sram3_init ( sram3_t *ctx, sram3_cfg_t *cfg );
 
err_t sram3_generic_write ( sram3_t *ctx, uint8_t reg, uint8_t *data_in, uint8_t len );
 
err_t sram3_generic_read ( sram3_t *ctx, uint8_t reg, uint8_t *data_out, uint8_t len );
 
void sram3_enable_write( sram3_t *ctx );
 
void sram3_disable_write( sram3_t *ctx );
 
uint8_t sram3_read_status( sram3_t *ctx );
 
void sram3_write_status( sram3_t *ctx, uint8_t status );
 
void sram3_protect_memory( sram3_t *ctx, uint8_t protect_range );
 
void sram3_enable_pdis( sram3_t *ctx );
 
void sram3_disable_pdis( sram3_t *ctx );
 
void sram3_recall( sram3_t *ctx );
 
void sram3_store( sram3_t *ctx );
 
void sram3_hibernate_start( sram3_t *ctx );
 
void sram3_hibernate_stop( sram3_t *ctx );
 
void sram3_hold( sram3_t *ctx );
 
void sram3_release_hold( sram3_t *ctx );
 
void sram3_read_serial( sram3_t *ctx, uint8_t *buf );
 
void sram3_write_serial( sram3_t *ctx, uint8_t *buf );
 
 
void sram3_read( sram3_t *ctx, uint32_t mem_adr, uint8_t *read_buf, uint8_t buf_size );
 
err_t sram3_secure_read( sram3_t *ctx, uint32_t mem_adr, uint8_t *read_buf, uint8_t buf_size );
 
void sram3_write( sram3_t *ctx, uint32_t mem_adr, uint8_t *write_buf, uint8_t buf_size );
 
err_t sram3_secure_write( sram3_t *ctx, uint32_t mem_adr, uint8_t *write_buf, uint8_t buf_size );
 
#ifdef __cplusplus
}
#endif
#endif // SRAM3_H
 
 // sram3
 
// ------------------------------------------------------------------------ END