mikroSDK Reference Manual
stm32f2xx_hal_rcc_ex.h
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1
20/* Define to prevent recursive inclusion -------------------------------------*/
21#ifndef __STM32F2xx_HAL_RCC_EX_H
22#define __STM32F2xx_HAL_RCC_EX_H
23
24#ifdef __cplusplus
25 extern "C" {
26#endif
27
28/* Includes ------------------------------------------------------------------*/
29#include "stm32f2xx_hal_def.h"
30
39/* Exported types ------------------------------------------------------------*/
46typedef struct
47{
48 uint32_t PLLI2SN;
52 uint32_t PLLI2SR;
56}RCC_PLLI2SInitTypeDef;
57
61typedef struct
62{
63 uint32_t PeriphClockSelection;
66 RCC_PLLI2SInitTypeDef PLLI2S;
69 uint32_t RTCClockSelection;
72 uint8_t TIMPresSelection;
75}RCC_PeriphCLKInitTypeDef;
80/* Exported constants --------------------------------------------------------*/
88#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001)
89#define RCC_PERIPHCLK_TIM ((uint32_t)0x00000002)
90#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000004)
91#define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x00000008)
92
100#define RCC_TIMPRES_DESACTIVATED ((uint8_t)0x00)
101#define RCC_TIMPRES_ACTIVATED ((uint8_t)0x01)
110/* Exported macro ------------------------------------------------------------*/
122#if defined(STM32F207xx) || defined(STM32F217xx)
123#define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \
124 __IO uint32_t tmpreg = 0x00; \
125 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
126 /* Delay after an RCC peripheral clock enabling */ \
127 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
128 UNUSED(tmpreg); \
129 } while(0)
130#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
131 __IO uint32_t tmpreg = 0x00; \
132 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
133 /* Delay after an RCC peripheral clock enabling */ \
134 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
135 UNUSED(tmpreg); \
136 } while(0)
137#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
138 __IO uint32_t tmpreg = 0x00; \
139 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
140 /* Delay after an RCC peripheral clock enabling */ \
141 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
142 UNUSED(tmpreg); \
143 } while(0)
144#define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \
145 __IO uint32_t tmpreg = 0x00; \
146 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
147 /* Delay after an RCC peripheral clock enabling */ \
148 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
149 UNUSED(tmpreg); \
150 } while(0)
151
152#define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
153#define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
154#define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
155#define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
156
164#define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_ETHMACEN))!= RESET)
165#define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_ETHMACTXEN))!= RESET)
166#define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_ETHMACRXEN))!= RESET)
167#define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_ETHMACPTPEN))!= RESET)
168#define __HAL_RCC_ETH_IS_CLK_ENABLED() (__HAL_RCC_ETHMAC_IS_CLK_ENABLED() && \
169 __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \
170 __HAL_RCC_ETHMACRX_IS_CLK_ENABLED())
171#define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_ETHMACEN))== RESET)
172#define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_ETHMACTXEN))== RESET)
173#define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_ETHMACRXEN))== RESET)
174#define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_ETHMACPTPEN))== RESET)
175#define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \
176 __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \
177 __HAL_RCC_ETHMACRX_IS_CLK_DISABLED())
185#define __HAL_RCC_ETH_CLK_ENABLE() do { \
186 __HAL_RCC_ETHMAC_CLK_ENABLE(); \
187 __HAL_RCC_ETHMACTX_CLK_ENABLE(); \
188 __HAL_RCC_ETHMACRX_CLK_ENABLE(); \
189 } while(0)
193#define __HAL_RCC_ETH_CLK_DISABLE() do { \
194 __HAL_RCC_ETHMACTX_CLK_DISABLE(); \
195 __HAL_RCC_ETHMACRX_CLK_DISABLE(); \
196 __HAL_RCC_ETHMAC_CLK_DISABLE(); \
197 } while(0)
198#endif /* STM32F207xx || STM32F217xx */
210#if defined(STM32F207xx) || defined(STM32F217xx)
211#define __HAL_RCC_DCMI_CLK_ENABLE() do { \
212 __IO uint32_t tmpreg = 0x00; \
213 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
214 /* Delay after an RCC peripheral clock enabling */ \
215 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
216 UNUSED(tmpreg); \
217 } while(0)
218
219#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
220#endif /* STM32F207xx || STM32F217xx */
221
222#if defined(STM32F215xx) || defined(STM32F217xx)
223#define __HAL_RCC_CRYP_CLK_ENABLE() do { \
224 __IO uint32_t tmpreg = 0x00; \
225 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
226 /* Delay after an RCC peripheral clock enabling */ \
227 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
228 UNUSED(tmpreg); \
229 } while(0)
230#define __HAL_RCC_HASH_CLK_ENABLE() do { \
231 __IO uint32_t tmpreg = 0x00; \
232 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
233 /* Delay after an RCC peripheral clock enabling */ \
234 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
235 UNUSED(tmpreg); \
236 } while(0)
237
238#define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
239#define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
240#endif /* STM32F215xx || STM32F217xx */
252#if defined(STM32F207xx) || defined(STM32F217xx)
253#define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR &(RCC_AHB2ENR_DCMIEN))!= RESET)
254#define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR &(RCC_AHB2ENR_DCMIEN))== RESET)
255#endif /* defined(STM32F207xx) || defined(STM32F217xx) */
256#if defined(STM32F215xx) || defined(STM32F217xx)
257#define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR &(RCC_AHB2ENR_CRYPEN))!= RESET)
258#define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR &(RCC_AHB2ENR_HASHEN))!= RESET)
259
260#define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR &(RCC_AHB2ENR_CRYPEN))== RESET)
261#define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR &(RCC_AHB2ENR_HASHEN))== RESET)
262#endif /* defined(STM32F215xx) || defined(STM32F217xx) */
271#if defined(STM32F207xx) || defined(STM32F217xx)
272#define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST))
273#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
274#endif /* STM32F207xx || STM32F217xx */
283#if defined(STM32F207xx) || defined(STM32F217xx)
284#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
285#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
286#endif /* STM32F207xx || STM32F217xx */
287
288#if defined(STM32F215xx) || defined(STM32F217xx)
289#define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))
290#define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))
291
292#define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
293#define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
294#endif /* STM32F215xx || STM32F217xx */
295
308#if defined(STM32F207xx) || defined(STM32F217xx)
309#define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN))
310#define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN))
311#define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN))
312#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN))
313
314#define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
315#define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
316#define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
317#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
318#endif /* STM32F207xx || STM32F217xx */
331#if defined(STM32F207xx) || defined(STM32F217xx)
332#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
333#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
334#endif /* STM32F207xx || STM32F217xx */
335
336#if defined(STM32F215xx) || defined(STM32F217xx)
337#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
338#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
339
340#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
341#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
342#endif /* STM32F215xx || STM32F217xx */
351/* Exported functions --------------------------------------------------------*/
359HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
360void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
361
362HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit);
363HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void);
371/* Private types -------------------------------------------------------------*/
372/* Private variables ---------------------------------------------------------*/
373/* Private constants ---------------------------------------------------------*/
382#define PLL_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
391/* Private macros ------------------------------------------------------------*/
398#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x0000000F))
399#define IS_RCC_PLLI2SN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
400#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
416#ifdef __cplusplus
417}
418#endif
419
420#endif /* __STM32F2xx_HAL_RCC_EX_H */
421
422/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition.
Definition stm32f1xx_hal_def.h:40
stm32f2xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
RCC_PLLI2SInitTypeDef
PLLI2S Clock structure definition
Definition stm32f2xx_hal_rcc_ex.h:47
RCC_PLLI2SInitTypeDef::PLLI2SN
uint32_t PLLI2SN
Definition stm32f2xx_hal_rcc_ex.h:48
RCC_PLLI2SInitTypeDef::PLLI2SR
uint32_t PLLI2SR
Definition stm32f2xx_hal_rcc_ex.h:52
RCC_PeriphCLKInitTypeDef
RCC extended clocks structure definition.
Definition stm32f1xx_hal_rcc_ex.h:284
RCC_PeriphCLKInitTypeDef::TIMPresSelection
uint8_t TIMPresSelection
Definition stm32f2xx_hal_rcc_ex.h:72
RCC_PeriphCLKInitTypeDef::PLLI2S
RCC_PLLI2SInitTypeDef PLLI2S
Definition stm32f2xx_hal_rcc_ex.h:66