TDC Registers List

List of registers of TDC Click driver. More...

Macros
#define	TDC_REG_ADR_CONFIG1   0x00
	TDC description register.
#define	TDC_REG_ADR_CONFIG2   0x01
#define	TDC_REG_ADR_INT_STATUS   0x02
#define	TDC_REG_ADR_INT_MASK   0x03
#define	TDC_REG_ADR_COARSE_CNTR_OVF_H   0x04
#define	TDC_REG_ADR_COARSE_CNTR_OVF_L   0x05
#define	TDC_REG_ADR_CLOCK_CNTR_OVF_H   0x06
#define	TDC_REG_ADR_CLOCK_CNTR_OVF_L   0x07
#define	TDC_REG_ADR_CLOCK_CNTR_STOP_MASK_H   0x08
#define	TDC_REG_ADR_CLOCK_CNTR_STOP_MASK_L   0x09
#define	TDC_REG_ADR_TIME1   0x10
#define	TDC_REG_ADR_CLOCK_COUNT1   0x11
#define	TDC_REG_ADR_TIME2   0x12
#define	TDC_REG_ADR_CLOCK_COUNT2   0x13
#define	TDC_REG_ADR_TIME3   0x14
#define	TDC_REG_ADR_CLOCK_COUNT3   0x15
#define	TDC_REG_ADR_TIME4   0x16
#define	TDC_REG_ADR_CLOCK_COUNT4   0x17
#define	TDC_REG_ADR_TIME5   0x18
#define	TDC_REG_ADR_CLOCK_COUNT5   0x19
#define	TDC_REG_ADR_CLOCK_COUNTX(num)   (TDC_REG_ADR_CLOCK_COUNT1+2*((num)-1))
#define	TDC_REG_ADR_TIME6   0x1A
#define	TDC_REG_ADR_TIMEX(num)   (TDC_REG_ADR_TIME1+2*((num)-1))
#define	TDC_REG_ADR_CALIBRATION1   0x1B
#define	TDC_REG_ADR_CALIBRATION2   0x1C
#define	TDC_REG_DEFAULTS_CONFIG2   0x40
#define	TDC_REG_DEFAULTS_INT_MASK   0x07
#define	TDC_REG_SHIFT_CONFIG1_FORCE_CAL   7
#define	TDC_REG_SHIFT_CONFIG1_PARITY_EN   6
#define	TDC_REG_SHIFT_CONFIG1_TRIGG_EDGE   5
#define	TDC_REG_SHIFT_CONFIG1_STOP_EDGE   4
#define	TDC_REG_SHIFT_CONFIG1_START_EDGE   3
#define	TDC_REG_SHIFT_CONFIG1_MEAS_MODE   1
#define	TDC_REG_SHIFT_CONFIG1_START_MEAS   0
#define	TDC_REG_VAL_CONFIG1_MEAS_MODE_MIN   1
#define	TDC_REG_VAL_CONFIG1_MEAS_MODE_MAX   2
#define	TDC_REG_VAL_CONFIG1_MEAS_MODE(num)   ((num)-1)
#define	TDC_REG_SHIFT_CONFIG2_CALIBRATION2_PERIODS   6
#define	TDC_REG_SHIFT_CONFIG2_AVG_CYCLES   3
#define	TDC_REG_SHIFT_CONFIG2_NUM_STOP   0
#define	TDC_REG_VAL_CONFIG2_CALIBRATION2_PERIODS_2   0
#define	TDC_REG_VAL_CONFIG2_CALIBRATION2_PERIODS_10   1
#define	TDC_REG_VAL_CONFIG2_CALIBRATION2_PERIODS_20   2
#define	TDC_REG_VAL_CONFIG2_CALIBRATION2_PERIODS_40   3
#define	TDC_REG_VAL_CONFIG2_AVG_CYCLES_MIN_VAL   0
#define	TDC_REG_VAL_CONFIG2_AVG_CYCLES_MIN   1 << TDC_REG_VAL_CONFIG2_AVG_CYCLES_MIN_VAL
#define	TDC_REG_VAL_CONFIG2_AVG_CYCLES_MAX_VAL   7
#define	TDC_REG_VAL_CONFIG2_AVG_CYCLES_MAX   1 << TDC_REG_VAL_CONFIG2_AVG_CYCLES_MAX_VAL
#define	TDC_REG_VAL_CONFIG2_NUM_STOP(num)   ((num)-1)
#define	TDC_REG_VAL_CONFIG2_NUM_STOP_MAX   5
#define	TDC_REG_SHIFT_INT_STATUS_MEAS_COMPLETE_FLAG   4
#define	TDC_REG_SHIFT_INT_STATUS_MEAS_STARTED_FLAG   3
#define	TDC_REG_SHIFT_INT_STATUS_CLOCK_CNTR_OVF_INT   2
#define	TDC_REG_SHIFT_INT_STATUS_COARSE_CNTR_OVF_INT   1
#define	TDC_REG_SHIFT_INT_STATUS_NEW_MEAS_INT   0
#define	TDC_REG_SHIFT_INT_MASK_CLOCK_CNTR_OVF_MASK   2
#define	TDC_REG_SHIFT_INT_MASK_COARSE_CNTR_OVF_MASK   1
#define	TDC_REG_SHIFT_INT_MASK_NEW_MEAS_MASK   0

Detailed Description

List of registers of TDC Click driver.

Macro Definition Documentation

TDC_REG_ADR_CALIBRATION1

#define TDC_REG_ADR_CALIBRATION1   0x1B

TDC_REG_ADR_CALIBRATION2

#define TDC_REG_ADR_CALIBRATION2   0x1C

TDC_REG_ADR_CLOCK_CNTR_OVF_H

#define TDC_REG_ADR_CLOCK_CNTR_OVF_H   0x06

TDC_REG_ADR_CLOCK_CNTR_OVF_L

#define TDC_REG_ADR_CLOCK_CNTR_OVF_L   0x07

TDC_REG_ADR_CLOCK_CNTR_STOP_MASK_H

#define TDC_REG_ADR_CLOCK_CNTR_STOP_MASK_H   0x08

TDC_REG_ADR_CLOCK_CNTR_STOP_MASK_L

#define TDC_REG_ADR_CLOCK_CNTR_STOP_MASK_L   0x09

TDC_REG_ADR_CLOCK_COUNT1

#define TDC_REG_ADR_CLOCK_COUNT1   0x11

TDC_REG_ADR_CLOCK_COUNT2

#define TDC_REG_ADR_CLOCK_COUNT2   0x13

TDC_REG_ADR_CLOCK_COUNT3

#define TDC_REG_ADR_CLOCK_COUNT3   0x15

TDC_REG_ADR_CLOCK_COUNT4

#define TDC_REG_ADR_CLOCK_COUNT4   0x17

TDC_REG_ADR_CLOCK_COUNT5

#define TDC_REG_ADR_CLOCK_COUNT5   0x19

TDC_REG_ADR_CLOCK_COUNTX

#define TDC_REG_ADR_CLOCK_COUNTX

(

num

)

(TDC_REG_ADR_CLOCK_COUNT1+2*((num)-1))

TDC_REG_ADR_COARSE_CNTR_OVF_H

#define TDC_REG_ADR_COARSE_CNTR_OVF_H   0x04

TDC_REG_ADR_COARSE_CNTR_OVF_L

#define TDC_REG_ADR_COARSE_CNTR_OVF_L   0x05

TDC_REG_ADR_CONFIG1

#define TDC_REG_ADR_CONFIG1   0x00

TDC description register.

Specified register for description of TDC Click driver.

TDC_REG_ADR_CONFIG2

#define TDC_REG_ADR_CONFIG2   0x01

TDC_REG_ADR_INT_MASK

#define TDC_REG_ADR_INT_MASK   0x03

TDC_REG_ADR_INT_STATUS

#define TDC_REG_ADR_INT_STATUS   0x02

TDC_REG_ADR_TIME1

#define TDC_REG_ADR_TIME1   0x10

TDC_REG_ADR_TIME2

#define TDC_REG_ADR_TIME2   0x12

TDC_REG_ADR_TIME3

#define TDC_REG_ADR_TIME3   0x14

TDC_REG_ADR_TIME4

#define TDC_REG_ADR_TIME4   0x16

TDC_REG_ADR_TIME5

#define TDC_REG_ADR_TIME5   0x18

TDC_REG_ADR_TIME6

#define TDC_REG_ADR_TIME6   0x1A

TDC_REG_ADR_TIMEX

#define TDC_REG_ADR_TIMEX

(

num

)

(TDC_REG_ADR_TIME1+2*((num)-1))

TDC_REG_DEFAULTS_CONFIG2

#define TDC_REG_DEFAULTS_CONFIG2   0x40

TDC_REG_DEFAULTS_INT_MASK

#define TDC_REG_DEFAULTS_INT_MASK   0x07

TDC_REG_SHIFT_CONFIG1_FORCE_CAL

#define TDC_REG_SHIFT_CONFIG1_FORCE_CAL   7

TDC_REG_SHIFT_CONFIG1_MEAS_MODE

#define TDC_REG_SHIFT_CONFIG1_MEAS_MODE   1

TDC_REG_SHIFT_CONFIG1_PARITY_EN

#define TDC_REG_SHIFT_CONFIG1_PARITY_EN   6

TDC_REG_SHIFT_CONFIG1_START_EDGE

#define TDC_REG_SHIFT_CONFIG1_START_EDGE   3

TDC_REG_SHIFT_CONFIG1_START_MEAS

#define TDC_REG_SHIFT_CONFIG1_START_MEAS   0

TDC_REG_SHIFT_CONFIG1_STOP_EDGE

#define TDC_REG_SHIFT_CONFIG1_STOP_EDGE   4

TDC_REG_SHIFT_CONFIG1_TRIGG_EDGE

#define TDC_REG_SHIFT_CONFIG1_TRIGG_EDGE   5

TDC_REG_SHIFT_CONFIG2_AVG_CYCLES

#define TDC_REG_SHIFT_CONFIG2_AVG_CYCLES   3

TDC_REG_SHIFT_CONFIG2_CALIBRATION2_PERIODS

#define TDC_REG_SHIFT_CONFIG2_CALIBRATION2_PERIODS   6

TDC_REG_SHIFT_CONFIG2_NUM_STOP

#define TDC_REG_SHIFT_CONFIG2_NUM_STOP   0

TDC_REG_SHIFT_INT_MASK_CLOCK_CNTR_OVF_MASK

#define TDC_REG_SHIFT_INT_MASK_CLOCK_CNTR_OVF_MASK   2

TDC_REG_SHIFT_INT_MASK_COARSE_CNTR_OVF_MASK

#define TDC_REG_SHIFT_INT_MASK_COARSE_CNTR_OVF_MASK   1

TDC_REG_SHIFT_INT_MASK_NEW_MEAS_MASK

#define TDC_REG_SHIFT_INT_MASK_NEW_MEAS_MASK   0

TDC_REG_SHIFT_INT_STATUS_CLOCK_CNTR_OVF_INT

#define TDC_REG_SHIFT_INT_STATUS_CLOCK_CNTR_OVF_INT   2

TDC_REG_SHIFT_INT_STATUS_COARSE_CNTR_OVF_INT

#define TDC_REG_SHIFT_INT_STATUS_COARSE_CNTR_OVF_INT   1

TDC_REG_SHIFT_INT_STATUS_MEAS_COMPLETE_FLAG

#define TDC_REG_SHIFT_INT_STATUS_MEAS_COMPLETE_FLAG   4

TDC_REG_SHIFT_INT_STATUS_MEAS_STARTED_FLAG

#define TDC_REG_SHIFT_INT_STATUS_MEAS_STARTED_FLAG   3

TDC_REG_SHIFT_INT_STATUS_NEW_MEAS_INT

#define TDC_REG_SHIFT_INT_STATUS_NEW_MEAS_INT   0

TDC_REG_VAL_CONFIG1_MEAS_MODE

#define TDC_REG_VAL_CONFIG1_MEAS_MODE

(

num

)

((num)-1)

TDC_REG_VAL_CONFIG1_MEAS_MODE_MAX

#define TDC_REG_VAL_CONFIG1_MEAS_MODE_MAX   2

TDC_REG_VAL_CONFIG1_MEAS_MODE_MIN

#define TDC_REG_VAL_CONFIG1_MEAS_MODE_MIN   1

TDC_REG_VAL_CONFIG2_AVG_CYCLES_MAX

#define TDC_REG_VAL_CONFIG2_AVG_CYCLES_MAX   1 << TDC_REG_VAL_CONFIG2_AVG_CYCLES_MAX_VAL

TDC_REG_VAL_CONFIG2_AVG_CYCLES_MAX_VAL

#define TDC_REG_VAL_CONFIG2_AVG_CYCLES_MAX_VAL   7

TDC_REG_VAL_CONFIG2_AVG_CYCLES_MIN

#define TDC_REG_VAL_CONFIG2_AVG_CYCLES_MIN   1 << TDC_REG_VAL_CONFIG2_AVG_CYCLES_MIN_VAL

TDC_REG_VAL_CONFIG2_AVG_CYCLES_MIN_VAL

#define TDC_REG_VAL_CONFIG2_AVG_CYCLES_MIN_VAL   0

TDC_REG_VAL_CONFIG2_CALIBRATION2_PERIODS_10

#define TDC_REG_VAL_CONFIG2_CALIBRATION2_PERIODS_10   1

TDC_REG_VAL_CONFIG2_CALIBRATION2_PERIODS_2

#define TDC_REG_VAL_CONFIG2_CALIBRATION2_PERIODS_2   0

TDC_REG_VAL_CONFIG2_CALIBRATION2_PERIODS_20

#define TDC_REG_VAL_CONFIG2_CALIBRATION2_PERIODS_20   2

TDC_REG_VAL_CONFIG2_CALIBRATION2_PERIODS_40

#define TDC_REG_VAL_CONFIG2_CALIBRATION2_PERIODS_40   3

TDC_REG_VAL_CONFIG2_NUM_STOP

#define TDC_REG_VAL_CONFIG2_NUM_STOP

(

num

)

((num)-1)

TDC_REG_VAL_CONFIG2_NUM_STOP_MAX

#define TDC_REG_VAL_CONFIG2_NUM_STOP_MAX   5