temphum12 2.0.0.0
Interrupt enable register

Macros

#define TEMPHUM12_INTE_DRDY_ENABLE   0x80
 
#define TEMPHUM12_INTE_DRDY_DISABLE   0x00
 
#define TEMPHUM12_INTE_TEMP_TH_ENABLE   0x40
 
#define TEMPHUM12_INTE_TEMP_TH_DISABLE   0x00
 
#define TEMPHUM12_INTE_TEMP_TL_ENABLE   0x20
 
#define TEMPHUM12_INTE_TEMP_TL_DISABLE   0x00
 
#define TEMPHUM12_INTE_HUM_TH_ENABLE   0x10
 
#define TEMPHUM12_INTE_HUM_TH_DISABLE   0x00
 
#define TEMPHUM12_INTE_HUM_TL_ENABLE   0x08
 
#define TEMPHUM12_INTE_HUM_TL_DISABLE   0x00
 

Detailed Description

Macro Definition Documentation

◆ TEMPHUM12_INTE_DRDY_DISABLE

#define TEMPHUM12_INTE_DRDY_DISABLE   0x00

◆ TEMPHUM12_INTE_DRDY_ENABLE

#define TEMPHUM12_INTE_DRDY_ENABLE   0x80

◆ TEMPHUM12_INTE_HUM_TH_DISABLE

#define TEMPHUM12_INTE_HUM_TH_DISABLE   0x00

◆ TEMPHUM12_INTE_HUM_TH_ENABLE

#define TEMPHUM12_INTE_HUM_TH_ENABLE   0x10

◆ TEMPHUM12_INTE_HUM_TL_DISABLE

#define TEMPHUM12_INTE_HUM_TL_DISABLE   0x00

◆ TEMPHUM12_INTE_HUM_TL_ENABLE

#define TEMPHUM12_INTE_HUM_TL_ENABLE   0x08

◆ TEMPHUM12_INTE_TEMP_TH_DISABLE

#define TEMPHUM12_INTE_TEMP_TH_DISABLE   0x00

◆ TEMPHUM12_INTE_TEMP_TH_ENABLE

#define TEMPHUM12_INTE_TEMP_TH_ENABLE   0x40

◆ TEMPHUM12_INTE_TEMP_TL_DISABLE

#define TEMPHUM12_INTE_TEMP_TL_DISABLE   0x00

◆ TEMPHUM12_INTE_TEMP_TL_ENABLE

#define TEMPHUM12_INTE_TEMP_TL_ENABLE   0x20