ultrasonic5 2.1.0.0
Macros
Ultrasonic 5 Registers Settings
Ultrasonic 5 Click Driver

Settings for registers of Ultrasonic 5 Click driver. More...

Macros

#define ULTRASONIC5_BPF_CONFIG_1_FC_TRIM_FRC   0x80
 Ultrasonic 5 BPF_CONFIG_1 register settings.
 
#define ULTRASONIC5_BPF_CONFIG_1_BYPASS   0x40
 
#define ULTRASONIC5_BPF_CONFIG_1_HPF_FREQ_MASK   0x3F
 
#define ULTRASONIC5_BPF_CONFIG_1_RESET   0x00
 
#define ULTRASONIC5_BPF_CONFIG_2_Q_SEL_4   0x00
 Ultrasonic 5 BPF_CONFIG_2 register settings.
 
#define ULTRASONIC5_BPF_CONFIG_2_Q_SEL_5   0x10
 
#define ULTRASONIC5_BPF_CONFIG_2_Q_SEL_2   0x20
 
#define ULTRASONIC5_BPF_CONFIG_2_Q_SEL_3   0x30
 
#define ULTRASONIC5_BPF_CONFIG_2_Q_SEL_MASK   0x30
 
#define ULTRASONIC5_BPF_CONFIG_2_FC_TRIM_MASK   0x0F
 
#define ULTRASONIC5_BPF_CONFIG_2_RESET   0x00
 
#define ULTRASONIC5_DEV_CTRL_1_LOGAMP_FRC   0x80
 Ultrasonic 5 DEV_CTRL_1 register settings.
 
#define ULTRASONIC5_DEV_CTRL_1_LOGAMP_SLP_ADJ_MASK   0x70
 
#define ULTRASONIC5_DEV_CTRL_1_LOGAMP_INT_ADJ_MASK   0x0F
 
#define ULTRASONIC5_DEV_CTRL_1_RESET   0x00
 
#define ULTRASONIC5_DEV_CTRL_2_LOGAMP_DIS_FIRST   0x80
 Ultrasonic 5 DEV_CTRL_2 register settings.
 
#define ULTRASONIC5_DEV_CTRL_2_LOGAMP_DIS_LAST   0x40
 
#define ULTRASONIC5_DEV_CTRL_2_VOUT_SCALE_SEL_5V   0x04
 
#define ULTRASONIC5_DEV_CTRL_2_LNA_GAIN_15V   0x00
 
#define ULTRASONIC5_DEV_CTRL_2_LNA_GAIN_10V   0x01
 
#define ULTRASONIC5_DEV_CTRL_2_LNA_GAIN_20V   0x02
 
#define ULTRASONIC5_DEV_CTRL_2_LNA_GAIN_12_5V   0x03
 
#define ULTRASONIC5_DEV_CTRL_2_LNA_GAIN_MASK   0x03
 
#define ULTRASONIC5_DEV_CTRL_2_RESET   0x00
 
#define ULTRASONIC5_DEV_CTRL_3_DRV_PLS_FLT_DT_64US   0x00
 Ultrasonic 5 DEV_CTRL_3 register settings.
 
#define ULTRASONIC5_DEV_CTRL_3_DRV_PLS_FLT_DT_48US   0x04
 
#define ULTRASONIC5_DEV_CTRL_3_DRV_PLS_FLT_DT_32US   0x08
 
#define ULTRASONIC5_DEV_CTRL_3_DRV_PLS_FLT_DT_24US   0x0C
 
#define ULTRASONIC5_DEV_CTRL_3_DRV_PLS_FLT_DT_16US   0x10
 
#define ULTRASONIC5_DEV_CTRL_3_DRV_PLS_FLT_DT_8US   0x14
 
#define ULTRASONIC5_DEV_CTRL_3_DRV_PLS_FLT_DT_4US   0x18
 
#define ULTRASONIC5_DEV_CTRL_3_DRV_PLS_FLT_DT_DIS   0x1C
 
#define ULTRASONIC5_DEV_CTRL_3_DRV_PLS_FLT_DT_MASK   0x1C
 
#define ULTRASONIC5_DEV_CTRL_3_IO_MODE_0   0x00
 
#define ULTRASONIC5_DEV_CTRL_3_IO_MODE_1   0x01
 
#define ULTRASONIC5_DEV_CTRL_3_IO_MODE_2   0x02
 
#define ULTRASONIC5_DEV_CTRL_3_IO_MODE_3   0x03
 
#define ULTRASONIC5_DEV_CTRL_3_IO_MODE_MASK   0x03
 
#define ULTRASONIC5_DEV_CTRL_3_RESET   0x00
 
#define ULTRASONIC5_VDRV_CTRL_DIS_VDRV_REG_LSTN   0x40
 Ultrasonic 5 VDRV_CTRL register settings.
 
#define ULTRASONIC5_VDRV_CTRL_VDRV_HI_Z   0x20
 
#define ULTRASONIC5_VDRV_CTRL_VDRV_CURR_LVL_20MA   0x10
 
#define ULTRASONIC5_VDRV_CTRL_VDRV_VOLT_LVL_5V   0x00
 
#define ULTRASONIC5_VDRV_CTRL_VDRV_VOLT_LVL_MASK   0x0F
 
#define ULTRASONIC5_VDRV_CTRL_RESET   0x20
 
#define ULTRASONIC5_ECHO_INT_CONFIG_CMP_EN   0x10
 Ultrasonic 5 ECHO_INT_CONFIG register settings.
 
#define ULTRASONIC5_ECHO_INT_CONFIG_THR_SEL_MASK   0x0F
 
#define ULTRASONIC5_ECHO_INT_CONFIG_RESET   0x07
 
#define ULTRASONIC5_ZC_CONFIG_CMP_EN   0x80
 Ultrasonic 5 ZC_CONFIG register settings.
 
#define ULTRASONIC5_ZC_CONFIG_EN_ECHO_INT   0x40
 
#define ULTRASONIC5_ZC_CONFIG_CMP_IN_SEL   0x20
 
#define ULTRASONIC5_ZC_CONFIG_CMP_STG_SEL_MASK   0x18
 
#define ULTRASONIC5_ZC_CONFIG_CMP_HYST_MASK   0x07
 
#define ULTRASONIC5_ZC_CONFIG_RESET   0x14
 
#define ULTRASONIC5_BURST_PULSE_HALF_BRG_MODE   0x80
 Ultrasonic 5 BURST_PULSE register settings.
 
#define ULTRASONIC5_BURST_PULSE_PRE_DRIVER_MODE   0x40
 
#define ULTRASONIC5_BURST_PULSE_BURST_PULSE_16   0x0F
 
#define ULTRASONIC5_BURST_PULSE_BURST_PULSE_MASK   0x3F
 
#define ULTRASONIC5_BURST_PULSE_RESET   0x00
 
#define ULTRASONIC5_TOF_CONFIG_SLEEP_MODE_EN   0x80
 Ultrasonic 5 TOF_CONFIG register settings.
 
#define ULTRASONIC5_TOF_CONFIG_STDBY_MODE_EN   0x40
 
#define ULTRASONIC5_TOF_CONFIG_VDRV_TRIGGER   0x02
 
#define ULTRASONIC5_TOF_CONFIG_CMD_TRIGGER   0x01
 
#define ULTRASONIC5_TOF_CONFIG_RESET   0x00
 
#define ULTRASONIC5_DEF_FREQ   40000
 Ultrasonic 5 default PWM settings.
 
#define ULTRASONIC5_DEF_DYTY   0.5f
 
#define ULTRASONIC5_DEVICE_ID   0xB9
 Ultrasonic 5 device ID.
 
#define ULTRASONIC5_ODD_PARITY   0x01
 Ultrasonic 5 ODD parity flag.
 
#define ULTRASONIC5_SET_DATA_SAMPLE_EDGE   SET_SPI_DATA_SAMPLE_EDGE
 Data sample selection.
 
#define ULTRASONIC5_SET_DATA_SAMPLE_MIDDLE   SET_SPI_DATA_SAMPLE_MIDDLE
 

Detailed Description

Settings for registers of Ultrasonic 5 Click driver.

Macro Definition Documentation

◆ ULTRASONIC5_BPF_CONFIG_1_BYPASS

#define ULTRASONIC5_BPF_CONFIG_1_BYPASS   0x40

◆ ULTRASONIC5_BPF_CONFIG_1_FC_TRIM_FRC

#define ULTRASONIC5_BPF_CONFIG_1_FC_TRIM_FRC   0x80

Ultrasonic 5 BPF_CONFIG_1 register settings.

Specified BPF_CONFIG_1 register settings of Ultrasonic 5 Click driver.

◆ ULTRASONIC5_BPF_CONFIG_1_HPF_FREQ_MASK

#define ULTRASONIC5_BPF_CONFIG_1_HPF_FREQ_MASK   0x3F

◆ ULTRASONIC5_BPF_CONFIG_1_RESET

#define ULTRASONIC5_BPF_CONFIG_1_RESET   0x00

◆ ULTRASONIC5_BPF_CONFIG_2_FC_TRIM_MASK

#define ULTRASONIC5_BPF_CONFIG_2_FC_TRIM_MASK   0x0F

◆ ULTRASONIC5_BPF_CONFIG_2_Q_SEL_2

#define ULTRASONIC5_BPF_CONFIG_2_Q_SEL_2   0x20

◆ ULTRASONIC5_BPF_CONFIG_2_Q_SEL_3

#define ULTRASONIC5_BPF_CONFIG_2_Q_SEL_3   0x30

◆ ULTRASONIC5_BPF_CONFIG_2_Q_SEL_4

#define ULTRASONIC5_BPF_CONFIG_2_Q_SEL_4   0x00

Ultrasonic 5 BPF_CONFIG_2 register settings.

Specified BPF_CONFIG_2 register settings of Ultrasonic 5 Click driver.

◆ ULTRASONIC5_BPF_CONFIG_2_Q_SEL_5

#define ULTRASONIC5_BPF_CONFIG_2_Q_SEL_5   0x10

◆ ULTRASONIC5_BPF_CONFIG_2_Q_SEL_MASK

#define ULTRASONIC5_BPF_CONFIG_2_Q_SEL_MASK   0x30

◆ ULTRASONIC5_BPF_CONFIG_2_RESET

#define ULTRASONIC5_BPF_CONFIG_2_RESET   0x00

◆ ULTRASONIC5_BURST_PULSE_BURST_PULSE_16

#define ULTRASONIC5_BURST_PULSE_BURST_PULSE_16   0x0F

◆ ULTRASONIC5_BURST_PULSE_BURST_PULSE_MASK

#define ULTRASONIC5_BURST_PULSE_BURST_PULSE_MASK   0x3F

◆ ULTRASONIC5_BURST_PULSE_HALF_BRG_MODE

#define ULTRASONIC5_BURST_PULSE_HALF_BRG_MODE   0x80

Ultrasonic 5 BURST_PULSE register settings.

Specified BURST_PULSE register settings of Ultrasonic 5 Click driver.

◆ ULTRASONIC5_BURST_PULSE_PRE_DRIVER_MODE

#define ULTRASONIC5_BURST_PULSE_PRE_DRIVER_MODE   0x40

◆ ULTRASONIC5_BURST_PULSE_RESET

#define ULTRASONIC5_BURST_PULSE_RESET   0x00

◆ ULTRASONIC5_DEF_DYTY

#define ULTRASONIC5_DEF_DYTY   0.5f

◆ ULTRASONIC5_DEF_FREQ

#define ULTRASONIC5_DEF_FREQ   40000

Ultrasonic 5 default PWM settings.

Specified setting for default PWM settings of Ultrasonic 5 Click driver.

◆ ULTRASONIC5_DEV_CTRL_1_LOGAMP_FRC

#define ULTRASONIC5_DEV_CTRL_1_LOGAMP_FRC   0x80

Ultrasonic 5 DEV_CTRL_1 register settings.

Specified DEV_CTRL_1 register settings of Ultrasonic 5 Click driver.

◆ ULTRASONIC5_DEV_CTRL_1_LOGAMP_INT_ADJ_MASK

#define ULTRASONIC5_DEV_CTRL_1_LOGAMP_INT_ADJ_MASK   0x0F

◆ ULTRASONIC5_DEV_CTRL_1_LOGAMP_SLP_ADJ_MASK

#define ULTRASONIC5_DEV_CTRL_1_LOGAMP_SLP_ADJ_MASK   0x70

◆ ULTRASONIC5_DEV_CTRL_1_RESET

#define ULTRASONIC5_DEV_CTRL_1_RESET   0x00

◆ ULTRASONIC5_DEV_CTRL_2_LNA_GAIN_10V

#define ULTRASONIC5_DEV_CTRL_2_LNA_GAIN_10V   0x01

◆ ULTRASONIC5_DEV_CTRL_2_LNA_GAIN_12_5V

#define ULTRASONIC5_DEV_CTRL_2_LNA_GAIN_12_5V   0x03

◆ ULTRASONIC5_DEV_CTRL_2_LNA_GAIN_15V

#define ULTRASONIC5_DEV_CTRL_2_LNA_GAIN_15V   0x00

◆ ULTRASONIC5_DEV_CTRL_2_LNA_GAIN_20V

#define ULTRASONIC5_DEV_CTRL_2_LNA_GAIN_20V   0x02

◆ ULTRASONIC5_DEV_CTRL_2_LNA_GAIN_MASK

#define ULTRASONIC5_DEV_CTRL_2_LNA_GAIN_MASK   0x03

◆ ULTRASONIC5_DEV_CTRL_2_LOGAMP_DIS_FIRST

#define ULTRASONIC5_DEV_CTRL_2_LOGAMP_DIS_FIRST   0x80

Ultrasonic 5 DEV_CTRL_2 register settings.

Specified DEV_CTRL_2 register settings of Ultrasonic 5 Click driver.

◆ ULTRASONIC5_DEV_CTRL_2_LOGAMP_DIS_LAST

#define ULTRASONIC5_DEV_CTRL_2_LOGAMP_DIS_LAST   0x40

◆ ULTRASONIC5_DEV_CTRL_2_RESET

#define ULTRASONIC5_DEV_CTRL_2_RESET   0x00

◆ ULTRASONIC5_DEV_CTRL_2_VOUT_SCALE_SEL_5V

#define ULTRASONIC5_DEV_CTRL_2_VOUT_SCALE_SEL_5V   0x04

◆ ULTRASONIC5_DEV_CTRL_3_DRV_PLS_FLT_DT_16US

#define ULTRASONIC5_DEV_CTRL_3_DRV_PLS_FLT_DT_16US   0x10

◆ ULTRASONIC5_DEV_CTRL_3_DRV_PLS_FLT_DT_24US

#define ULTRASONIC5_DEV_CTRL_3_DRV_PLS_FLT_DT_24US   0x0C

◆ ULTRASONIC5_DEV_CTRL_3_DRV_PLS_FLT_DT_32US

#define ULTRASONIC5_DEV_CTRL_3_DRV_PLS_FLT_DT_32US   0x08

◆ ULTRASONIC5_DEV_CTRL_3_DRV_PLS_FLT_DT_48US

#define ULTRASONIC5_DEV_CTRL_3_DRV_PLS_FLT_DT_48US   0x04

◆ ULTRASONIC5_DEV_CTRL_3_DRV_PLS_FLT_DT_4US

#define ULTRASONIC5_DEV_CTRL_3_DRV_PLS_FLT_DT_4US   0x18

◆ ULTRASONIC5_DEV_CTRL_3_DRV_PLS_FLT_DT_64US

#define ULTRASONIC5_DEV_CTRL_3_DRV_PLS_FLT_DT_64US   0x00

Ultrasonic 5 DEV_CTRL_3 register settings.

Specified DEV_CTRL_3 register settings of Ultrasonic 5 Click driver.

◆ ULTRASONIC5_DEV_CTRL_3_DRV_PLS_FLT_DT_8US

#define ULTRASONIC5_DEV_CTRL_3_DRV_PLS_FLT_DT_8US   0x14

◆ ULTRASONIC5_DEV_CTRL_3_DRV_PLS_FLT_DT_DIS

#define ULTRASONIC5_DEV_CTRL_3_DRV_PLS_FLT_DT_DIS   0x1C

◆ ULTRASONIC5_DEV_CTRL_3_DRV_PLS_FLT_DT_MASK

#define ULTRASONIC5_DEV_CTRL_3_DRV_PLS_FLT_DT_MASK   0x1C

◆ ULTRASONIC5_DEV_CTRL_3_IO_MODE_0

#define ULTRASONIC5_DEV_CTRL_3_IO_MODE_0   0x00

◆ ULTRASONIC5_DEV_CTRL_3_IO_MODE_1

#define ULTRASONIC5_DEV_CTRL_3_IO_MODE_1   0x01

◆ ULTRASONIC5_DEV_CTRL_3_IO_MODE_2

#define ULTRASONIC5_DEV_CTRL_3_IO_MODE_2   0x02

◆ ULTRASONIC5_DEV_CTRL_3_IO_MODE_3

#define ULTRASONIC5_DEV_CTRL_3_IO_MODE_3   0x03

◆ ULTRASONIC5_DEV_CTRL_3_IO_MODE_MASK

#define ULTRASONIC5_DEV_CTRL_3_IO_MODE_MASK   0x03

◆ ULTRASONIC5_DEV_CTRL_3_RESET

#define ULTRASONIC5_DEV_CTRL_3_RESET   0x00

◆ ULTRASONIC5_DEVICE_ID

#define ULTRASONIC5_DEVICE_ID   0xB9

Ultrasonic 5 device ID.

Specified device ID of Ultrasonic 5 Click driver.

◆ ULTRASONIC5_ECHO_INT_CONFIG_CMP_EN

#define ULTRASONIC5_ECHO_INT_CONFIG_CMP_EN   0x10

Ultrasonic 5 ECHO_INT_CONFIG register settings.

Specified ECHO_INT_CONFIG register settings of Ultrasonic 5 Click driver.

◆ ULTRASONIC5_ECHO_INT_CONFIG_RESET

#define ULTRASONIC5_ECHO_INT_CONFIG_RESET   0x07

◆ ULTRASONIC5_ECHO_INT_CONFIG_THR_SEL_MASK

#define ULTRASONIC5_ECHO_INT_CONFIG_THR_SEL_MASK   0x0F

◆ ULTRASONIC5_ODD_PARITY

#define ULTRASONIC5_ODD_PARITY   0x01

Ultrasonic 5 ODD parity flag.

Specified flag for ODD parity of Ultrasonic 5 Click driver.

◆ ULTRASONIC5_SET_DATA_SAMPLE_EDGE

#define ULTRASONIC5_SET_DATA_SAMPLE_EDGE   SET_SPI_DATA_SAMPLE_EDGE

Data sample selection.

This macro sets data samples for SPI modules.

Note
Available only on Microchip PIC family devices. This macro will set data sampling for all SPI modules on MCU. Can be overwritten with ultrasonic5_init which will set SET_SPI_DATA_SAMPLE_MIDDLE by default on the mapped mikrobus.

◆ ULTRASONIC5_SET_DATA_SAMPLE_MIDDLE

#define ULTRASONIC5_SET_DATA_SAMPLE_MIDDLE   SET_SPI_DATA_SAMPLE_MIDDLE

◆ ULTRASONIC5_TOF_CONFIG_CMD_TRIGGER

#define ULTRASONIC5_TOF_CONFIG_CMD_TRIGGER   0x01

◆ ULTRASONIC5_TOF_CONFIG_RESET

#define ULTRASONIC5_TOF_CONFIG_RESET   0x00

◆ ULTRASONIC5_TOF_CONFIG_SLEEP_MODE_EN

#define ULTRASONIC5_TOF_CONFIG_SLEEP_MODE_EN   0x80

Ultrasonic 5 TOF_CONFIG register settings.

Specified TOF_CONFIG register settings of Ultrasonic 5 Click driver.

◆ ULTRASONIC5_TOF_CONFIG_STDBY_MODE_EN

#define ULTRASONIC5_TOF_CONFIG_STDBY_MODE_EN   0x40

◆ ULTRASONIC5_TOF_CONFIG_VDRV_TRIGGER

#define ULTRASONIC5_TOF_CONFIG_VDRV_TRIGGER   0x02

◆ ULTRASONIC5_VDRV_CTRL_DIS_VDRV_REG_LSTN

#define ULTRASONIC5_VDRV_CTRL_DIS_VDRV_REG_LSTN   0x40

Ultrasonic 5 VDRV_CTRL register settings.

Specified VDRV_CTRL register settings of Ultrasonic 5 Click driver.

◆ ULTRASONIC5_VDRV_CTRL_RESET

#define ULTRASONIC5_VDRV_CTRL_RESET   0x20

◆ ULTRASONIC5_VDRV_CTRL_VDRV_CURR_LVL_20MA

#define ULTRASONIC5_VDRV_CTRL_VDRV_CURR_LVL_20MA   0x10

◆ ULTRASONIC5_VDRV_CTRL_VDRV_HI_Z

#define ULTRASONIC5_VDRV_CTRL_VDRV_HI_Z   0x20

◆ ULTRASONIC5_VDRV_CTRL_VDRV_VOLT_LVL_5V

#define ULTRASONIC5_VDRV_CTRL_VDRV_VOLT_LVL_5V   0x00

◆ ULTRASONIC5_VDRV_CTRL_VDRV_VOLT_LVL_MASK

#define ULTRASONIC5_VDRV_CTRL_VDRV_VOLT_LVL_MASK   0x0F

◆ ULTRASONIC5_ZC_CONFIG_CMP_EN

#define ULTRASONIC5_ZC_CONFIG_CMP_EN   0x80

Ultrasonic 5 ZC_CONFIG register settings.

Specified ZC_CONFIG register settings of Ultrasonic 5 Click driver.

◆ ULTRASONIC5_ZC_CONFIG_CMP_HYST_MASK

#define ULTRASONIC5_ZC_CONFIG_CMP_HYST_MASK   0x07

◆ ULTRASONIC5_ZC_CONFIG_CMP_IN_SEL

#define ULTRASONIC5_ZC_CONFIG_CMP_IN_SEL   0x20

◆ ULTRASONIC5_ZC_CONFIG_CMP_STG_SEL_MASK

#define ULTRASONIC5_ZC_CONFIG_CMP_STG_SEL_MASK   0x18

◆ ULTRASONIC5_ZC_CONFIG_EN_ECHO_INT

#define ULTRASONIC5_ZC_CONFIG_EN_ECHO_INT   0x40

◆ ULTRASONIC5_ZC_CONFIG_RESET

#define ULTRASONIC5_ZC_CONFIG_RESET   0x14