Macros
#define	UV4_PART_ID_REG 0x00

#define	UV4_HW_ID_REG 0x01

#define	UV4_REV_ID_REG 0x02

#define	UV4_INFO_0_REG 0x03

#define	UV4_INFO_1_REG 0x04

#define	UV4_INPUT_3_REG 0x07

#define	UV4_INPUT_2_REG 0x08

#define	UV4_INPUT_1_REG 0x09

#define	UV4_INPUT_0_REG 0x0A

#define	UV4_COMMAND_REG 0x0B

#define	UV4_IRQ_ENABLE_REG 0x0F

#define	UV4_RESPONSE_1_REG 0x10

#define	UV4_RESPONSE_0_REG 0x11

#define	UV4_IRQ_STATUS_REG 0x12

#define	UV4_OUTPUT_0_REG 0x13

#define	UV4_OUTPUT_1_REG 0x14

#define	UV4_OUTPUT_2_REG 0x15

#define	UV4_OUTPUT_3_REG 0x16

#define	UV4_OUTPUT_4_REG 0x17

#define	UV4_OUTPUT_5_REG 0x18

#define	UV4_OUTPUT_6_REG 0x19

#define	UV4_OUTPUT_7_REG 0x1A

#define	UV4_OUTPUT_8_REG 0x1B

#define	UV4_OUTPUT_9_REG 0x1C

#define	UV4_OUTPUT_10_REG 0x1D

#define	UV4_OUTPUT_11_REG 0x1E

#define	UV4_OUTPUT_12_REG 0x1F

#define	UV4_OUTPUT_13_REG 0x20

#define	UV4_OUTPUT_14_REG 0x21

#define	UV4_OUTPUT_15_REG 0x22

#define	UV4_OUTPUT_16_REG 0x23

#define	UV4_OUTPUT_17_REG 0x24

#define	UV4_OUTPUT_18_REG 0x25

#define	UV4_OUTPUT_19_REG 0x26

#define	UV4_OUTPUT_20_REG 0x27

#define	UV4_OUTPUT_21_REG 0x28

#define	UV4_OUTPUT_22_REG 0x29

#define	UV4_OUTPUT_23_REG 0x2A

#define	UV4_OUTPUT_24_REG 0x2B

#define	UV4_OUTPUT_25_REG 0x2C

Detailed Description

Macro Definition Documentation

◆ UV4_COMMAND_REG

#define UV4_COMMAND_REG 0x0B

◆ UV4_HW_ID_REG

#define UV4_HW_ID_REG 0x01

◆ UV4_INFO_0_REG

#define UV4_INFO_0_REG 0x03

◆ UV4_INFO_1_REG

#define UV4_INFO_1_REG 0x04

◆ UV4_INPUT_0_REG

#define UV4_INPUT_0_REG 0x0A

◆ UV4_INPUT_1_REG

#define UV4_INPUT_1_REG 0x09

◆ UV4_INPUT_2_REG

#define UV4_INPUT_2_REG 0x08

◆ UV4_INPUT_3_REG

#define UV4_INPUT_3_REG 0x07

◆ UV4_IRQ_ENABLE_REG

#define UV4_IRQ_ENABLE_REG 0x0F

◆ UV4_IRQ_STATUS_REG

#define UV4_IRQ_STATUS_REG 0x12

◆ UV4_OUTPUT_0_REG

#define UV4_OUTPUT_0_REG 0x13

◆ UV4_OUTPUT_10_REG

#define UV4_OUTPUT_10_REG 0x1D

◆ UV4_OUTPUT_11_REG

#define UV4_OUTPUT_11_REG 0x1E

◆ UV4_OUTPUT_12_REG

#define UV4_OUTPUT_12_REG 0x1F

◆ UV4_OUTPUT_13_REG

#define UV4_OUTPUT_13_REG 0x20

◆ UV4_OUTPUT_14_REG

#define UV4_OUTPUT_14_REG 0x21

◆ UV4_OUTPUT_15_REG

#define UV4_OUTPUT_15_REG 0x22

◆ UV4_OUTPUT_16_REG

#define UV4_OUTPUT_16_REG 0x23

◆ UV4_OUTPUT_17_REG

#define UV4_OUTPUT_17_REG 0x24

◆ UV4_OUTPUT_18_REG

#define UV4_OUTPUT_18_REG 0x25

◆ UV4_OUTPUT_19_REG

#define UV4_OUTPUT_19_REG 0x26

◆ UV4_OUTPUT_1_REG

#define UV4_OUTPUT_1_REG 0x14

◆ UV4_OUTPUT_20_REG

#define UV4_OUTPUT_20_REG 0x27

◆ UV4_OUTPUT_21_REG

#define UV4_OUTPUT_21_REG 0x28

◆ UV4_OUTPUT_22_REG

#define UV4_OUTPUT_22_REG 0x29

◆ UV4_OUTPUT_23_REG

#define UV4_OUTPUT_23_REG 0x2A

◆ UV4_OUTPUT_24_REG

#define UV4_OUTPUT_24_REG 0x2B

◆ UV4_OUTPUT_25_REG

#define UV4_OUTPUT_25_REG 0x2C

◆ UV4_OUTPUT_2_REG

#define UV4_OUTPUT_2_REG 0x15

◆ UV4_OUTPUT_3_REG

#define UV4_OUTPUT_3_REG 0x16

◆ UV4_OUTPUT_4_REG

#define UV4_OUTPUT_4_REG 0x17

◆ UV4_OUTPUT_5_REG

#define UV4_OUTPUT_5_REG 0x18

◆ UV4_OUTPUT_6_REG

#define UV4_OUTPUT_6_REG 0x19

◆ UV4_OUTPUT_7_REG

#define UV4_OUTPUT_7_REG 0x1A

◆ UV4_OUTPUT_8_REG

#define UV4_OUTPUT_8_REG 0x1B

◆ UV4_OUTPUT_9_REG

#define UV4_OUTPUT_9_REG 0x1C

◆ UV4_PART_ID_REG

#define UV4_PART_ID_REG 0x00

◆ UV4_RESPONSE_0_REG

#define UV4_RESPONSE_0_REG 0x11

◆ UV4_RESPONSE_1_REG

#define UV4_RESPONSE_1_REG 0x10

◆ UV4_REV_ID_REG

#define UV4_REV_ID_REG 0x02

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