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uwb2 2.1.0.0
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Settings for registers of UWB 2 Click driver. More...
Settings for registers of UWB 2 Click driver.
| #define UWB2_BIAS_CTRL_MASK 0x1F |
UWB 2 BIAS_CTRL register settings.
Specified BIAS_CTRL register settings of UWB 2 Click driver.
| #define UWB2_CHAN_CTRL_RF_CHAN_MASK 0x0001u |
| #define UWB2_CHAN_CTRL_RX_PCODE_MASK 0x1F00u |
UWB 2 CHAN_CTRL register settings.
Specified CHAN_CTRL register settings of UWB 2 Click driver.
| #define UWB2_CHAN_CTRL_SFD_TYPE_DW_16 0x0004u |
| #define UWB2_CHAN_CTRL_SFD_TYPE_DW_8 0x0002u |
| #define UWB2_CHAN_CTRL_SFD_TYPE_IEEE_4A 0x0000u |
| #define UWB2_CHAN_CTRL_SFD_TYPE_IEEE_4Z 0x0006u |
| #define UWB2_CHAN_CTRL_SFD_TYPE_MASK 0x0006u |
| #define UWB2_CHAN_CTRL_TX_PCODE_MASK 0x00F8u |
| #define UWB2_CHANNEL_5 0x05 |
UWB 2 chip configuration settings.
Specified chip configuration settings of UWB 2 Click driver.
| #define UWB2_CHANNEL_9 0x09 |
| #define UWB2_CLK_CTRL_ACC_CLK_EN_MASK 0x00000040ul |
| #define UWB2_CLK_CTRL_ACC_MCLK_EN_MASK 0x00008000ul |
| #define UWB2_CLK_CTRL_CIA_CLK_EN_MASK 0x00000100ul |
| #define UWB2_CLK_CTRL_GPIO_CLK_EN_MASK 0x00010000ul |
| #define UWB2_CLK_CTRL_GPIO_DCLK_EN_MASK 0x00040000ul |
| #define UWB2_CLK_CTRL_GPIO_DRST_N_MASK 0x00080000ul |
| #define UWB2_CLK_CTRL_LP_CLK_EN_MASK 0x00800000ul |
UWB 2 CLK_CTRL register settings.
Specified CLK_CTRL register settings of UWB 2 Click driver.
| #define UWB2_CLK_CTRL_RESERVED_BITS 0xF0300200ul |
| #define UWB2_CLK_CTRL_RX_CLK_AUTO 0x00000000ul |
| #define UWB2_CLK_CTRL_RX_CLK_FORCE 0x00000004ul |
| #define UWB2_CLK_CTRL_RX_CLK_MASK 0x0000000Cul |
| #define UWB2_CLK_CTRL_SAR_CLK_EN_MASK 0x00000400ul |
| #define UWB2_CLK_CTRL_SYS_CLK_AUTO 0x00000000ul |
| #define UWB2_CLK_CTRL_SYS_CLK_FORCE_FC 0x00000003ul |
| #define UWB2_CLK_CTRL_SYS_CLK_FORCE_FC_4 0x00000001ul |
| #define UWB2_CLK_CTRL_SYS_CLK_FORCE_PLL 0x00000002ul |
| #define UWB2_CLK_CTRL_SYS_CLK_MASK 0x00000003ul |
| #define UWB2_CLK_CTRL_TX_CLK_AUTO 0x00000000ul |
| #define UWB2_CLK_CTRL_TX_CLK_FORCE 0x00000010ul |
| #define UWB2_CLK_CTRL_TX_CLK_MASK 0x00000030ul |
| #define UWB2_DATA_RATE_6800KBS 0x01 |
| #define UWB2_DATA_RATE_850KBS 0x00 |
| #define UWB2_DEFAULT_CHANNEL UWB2_CHANNEL_5 |
UWB 2 chip default configuration.
Specified chip default configuration of UWB 2 Click driver.
| #define UWB2_DEFAULT_DATA_RATE UWB2_DATA_RATE_6800KBS |
| #define UWB2_DEFAULT_PAC UWB2_PAC_SIZE_8 |
| #define UWB2_DEFAULT_RX_CODE UWB2_RX_CODE_9 |
| #define UWB2_DEFAULT_SFD_TO ( 128 + 1 + 8 - 8 ) |
| #define UWB2_DEFAULT_SFD_TYPE UWB2_SFD_TYPE_DW_8 |
| #define UWB2_DEFAULT_TX_CODE UWB2_TX_CODE_9 |
| #define UWB2_DEFAULT_TX_PLEN UWB2_TX_PLEN_128 |
| #define UWB2_DEV_ID 0xDECA0302ul |
UWB 2 device ID value.
Specified device ID value of UWB 2 Click driver.
| #define UWB2_DEV_ID_MODEL_MASK 0x0000FF00ul |
| #define UWB2_DEV_ID_REV_MASK 0x0000000Ful |
| #define UWB2_DEV_ID_RIDTAG_MASK 0xFFFF0000ul |
| #define UWB2_DEV_ID_VER_MASK 0x000000F0ul |
| #define UWB2_DIAG_TMC_CIA_RUN_MASK 0x04000000ul |
UWB 2 DIAG_TMC register settings.
Specified DIAG_TMC register settings of UWB 2 Click driver.
| #define UWB2_DIAG_TMC_CIA_WDEN_MASK 0x01000000ul |
| #define UWB2_DIAG_TMC_HIRQ_POL_MASK 0x00200000ul |
| #define UWB2_DIAG_TMC_TX_PSTM_MASK 0x00000010ul |
| #define UWB2_DTUNE_0_DTOB4_MASK 0x0010u |
UWB 2 DTUNE_0 register settings.
Specified DTUNE_0 register settings of UWB 2 Click driver.
| #define UWB2_DTUNE_0_PAC_MASK 0x0003u |
| #define UWB2_DTUNE_0_RESERVED_BITS 0x100Cu |
| #define UWB2_DTUNE_3_DEFAULT 0xAF5F584Cul |
UWB 2 DTUNE_3 register settings.
Specified DTUNE_3 register settings of UWB 2 Click driver.
| #define UWB2_DTUNE_3_OPTIMAL 0xAF5F35CCul |
| #define UWB2_DTUNE_4_RX_SFD_HLDOFF 0x20000000ul |
UWB 2 DTUNE_4 register settings.
Specified DTUNE_4 register settings of UWB 2 Click driver.
| #define UWB2_DTUNE_4_RX_SFD_HLDOFF_DEFAULT 0x14000000ul |
| #define UWB2_DTUNE_4_RX_SFD_HLDOFF_MASK 0xFF000000ul |
| #define UWB2_GPIO_MODE_MSGP0_GPIO0 0x00000000ul |
| #define UWB2_GPIO_MODE_MSGP0_MASK 0x00000007ul |
| #define UWB2_GPIO_MODE_MSGP0_PDOA_SW_0 0x00000002ul |
| #define UWB2_GPIO_MODE_MSGP0_RXOKLED 0x00000001ul |
| #define UWB2_GPIO_MODE_MSGP1_GPIO1 0x00000000ul |
| #define UWB2_GPIO_MODE_MSGP1_MASK 0x00000038ul |
| #define UWB2_GPIO_MODE_MSGP1_PDOA_SW_1 0x00000010ul |
| #define UWB2_GPIO_MODE_MSGP1_SFDLED 0x00000008ul |
| #define UWB2_GPIO_MODE_MSGP2_GPIO2 0x00000000ul |
| #define UWB2_GPIO_MODE_MSGP2_MASK 0x000001C0ul |
| #define UWB2_GPIO_MODE_MSGP2_PDOA_SW_2 0x00000080ul |
| #define UWB2_GPIO_MODE_MSGP2_RXLED 0x00000040ul |
| #define UWB2_GPIO_MODE_MSGP3_GPIO3 0x00000000ul |
| #define UWB2_GPIO_MODE_MSGP3_MASK 0x00000E00ul |
| #define UWB2_GPIO_MODE_MSGP3_PDOA_SW_3 0x00000400ul |
| #define UWB2_GPIO_MODE_MSGP3_TXLED 0x00000200ul |
| #define UWB2_GPIO_MODE_MSGP4_EXTPA 0x00001000ul |
| #define UWB2_GPIO_MODE_MSGP4_GPIO4 0x00000000ul |
| #define UWB2_GPIO_MODE_MSGP4_IRQ 0x00002000ul |
| #define UWB2_GPIO_MODE_MSGP4_MASK 0x00007000ul |
| #define UWB2_GPIO_MODE_MSGP5_EXTTXE 0x00008000ul |
| #define UWB2_GPIO_MODE_MSGP5_GPIO5 0x00000000ul |
| #define UWB2_GPIO_MODE_MSGP5_MASK 0x00038000ul |
| #define UWB2_GPIO_MODE_MSGP6_EXTRXE 0x00040000ul |
| #define UWB2_GPIO_MODE_MSGP6_GPIO6 0x00000000ul |
| #define UWB2_GPIO_MODE_MSGP6_MASK 0x001C0000ul |
| #define UWB2_GPIO_MODE_MSGP7_GPIO7 0x00200000ul |
| #define UWB2_GPIO_MODE_MSGP7_MASK 0x00E00000ul |
| #define UWB2_GPIO_MODE_MSGP7_SYNC 0x00000000ul |
| #define UWB2_GPIO_MODE_MSGP8_GPIO8 0x01000000ul |
UWB 2 GPIO_MODE register settings.
Specified GPIO_MODE register settings of UWB 2 Click driver.
| #define UWB2_GPIO_MODE_MSGP8_IRQ 0x00000000ul |
| #define UWB2_GPIO_MODE_MSGP8_MASK 0x07000000ul |
| #define UWB2_IC_STATE_IDLE 1 |
| #define UWB2_IC_STATE_IDLE_RC 2 |
| #define UWB2_IC_STATE_INIT 0 |
UWB 2 IC state settings.
Specified IC state settings of UWB 2 Click driver.
| #define UWB2_LDO_CTRL_VDDHVTX_EN_MASK 0x00000800ul |
| #define UWB2_LDO_CTRL_VDDHVTX_VREF_MASK 0x08000000ul |
UWB 2 LDO_CTRL register settings.
Specified LDO_CTRL register settings of UWB 2 Click driver.
| #define UWB2_LDO_CTRL_VDDIF2_EN_MASK 0x00000100ul |
| #define UWB2_LDO_CTRL_VDDMS1_EN_MASK 0x00000001ul |
| #define UWB2_LDO_CTRL_VDDMS2_EN_MASK 0x00000002ul |
| #define UWB2_LDO_CTRL_VDDMS3_EN_MASK 0x00000004ul |
| #define UWB2_LDO_CTRL_VDDPLL_EN_MASK 0x00000010ul |
| #define UWB2_LDO_CTRL_VDDTX1_EN_MASK 0x00000020ul |
| #define UWB2_LDO_CTRL_VDDTX1_VREF_MASK 0x00200000ul |
| #define UWB2_LDO_CTRL_VDDTX2_EN_MASK 0x00000040ul |
| #define UWB2_LDO_CTRL_VDDTX2_VREF_MASK 0x00400000ul |
| #define UWB2_LDO_RLOAD_OPTIMAL 0x14 |
UWB 2 LDO_RLOAD register settings.
Specified LDO_RLOAD register settings of UWB 2 Click driver.
| #define UWB2_LED_CTRL_BLINK_EN_MASK 0x00000100ul |
| #define UWB2_LED_CTRL_BLINK_TIM_200MS 0x00000010ul |
| #define UWB2_LED_CTRL_BLINK_TIM_400MS 0x00000020ul |
| #define UWB2_LED_CTRL_BLINK_TIM_MASK 0x000000FFul |
| #define UWB2_LED_CTRL_FORCE_TRIG_MASK 0x000F0000ul |
UWB 2 LED_CTRL register settings.
Specified LED_CTRL register settings of UWB 2 Click driver.
| #define UWB2_MASK_ALL_16 0xFFFFu |
| #define UWB2_MASK_ALL_32 0xFFFFFFFFul |
UWB 2 modify register mask setting.
Specified modify register mask setting of UWB 2 Click driver.
| #define UWB2_MASK_ALL_8 0xFF |
| #define UWB2_MASK_NONE_16 0x0000u |
| #define UWB2_MASK_NONE_32 0x00000000ul |
| #define UWB2_MASK_NONE_8 0x00 |
| #define UWB2_OTP_CFG_BIAS_KICK_MASK 0x0100u |
| #define UWB2_OTP_CFG_DGC_KICK_MASK 0x0040u |
| #define UWB2_OTP_CFG_DGC_SEL_MASK 0x2000u |
UWB 2 OTP_CFG register settings.
Specified OTP_CFG register settings of UWB 2 Click driver.
| #define UWB2_OTP_CFG_LDO_KICK_MASK 0x0080u |
| #define UWB2_OTP_CFG_OPS_KICK_MASK 0x0400u |
| #define UWB2_OTP_CFG_OPS_SEL_LONG 0x0000u |
| #define UWB2_OTP_CFG_OPS_SEL_MASK 0x1800u |
| #define UWB2_OTP_CFG_OPS_SEL_SHORT 0x1000u |
| #define UWB2_OTP_CFG_OTP_MAN_MASK 0x0001u |
| #define UWB2_OTP_CFG_OTP_READ_MASK 0x0002u |
| #define UWB2_OTP_CFG_OTP_WRITE_MASK 0x0004u |
| #define UWB2_OTP_CFG_OTP_WRITE_MR_MASK 0x0008u |
| #define UWB2_PAC_SIZE_16 0x01 |
| #define UWB2_PAC_SIZE_32 0x02 |
| #define UWB2_PAC_SIZE_4 0x03 |
| #define UWB2_PAC_SIZE_8 0x00 |
| #define UWB2_PLL_CAL_CAL_EN_MASK 0x0100u |
UWB 2 PLL_CAL register settings.
Specified PLL_CAL register settings of UWB 2 Click driver.
| #define UWB2_PLL_CAL_OPTIMAL 0x0081u |
| #define UWB2_PLL_CAL_PLL_CFG_LD_MASK 0x0030u |
| #define UWB2_PLL_CAL_RESERVED_BITS 0x0001u |
| #define UWB2_PLL_CAL_USE_OLD_MASK 0x0002u |
| #define UWB2_PLL_CFG_CHANNEL_5 0x1F3Cu |
UWB 2 PLL_CFG register settings.
Specified PLL_CFG register settings of UWB 2 Click driver.
| #define UWB2_PLL_CFG_CHANNEL_9 0x0F3Cu |
| #define UWB2_RF_TX_CTRL_1_OPTIMAL 0x0E |
UWB 2 RF_TX_CTRL_1 register settings.
Specified RF_TX_CTRL_1 register settings of UWB 2 Click driver.
| #define UWB2_RF_TX_CTRL_2_CHANNEL_5 0x1C071134ul |
UWB 2 RF_TX_CTRL_2 register settings.
Specified RF_TX_CTRL_2 register settings of UWB 2 Click driver.
| #define UWB2_RF_TX_CTRL_2_CHANNEL_9 0x1C010034ul |
| #define UWB2_RX_CAL_CAL_EN_MASK 0x00000010ul |
| #define UWB2_RX_CAL_CAL_MODE_CALIBRATION 0x00000001ul |
| #define UWB2_RX_CAL_CAL_MODE_MASK 0x00000003ul |
| #define UWB2_RX_CAL_CAL_MODE_NORMAL 0x00000000ul |
| #define UWB2_RX_CAL_COMP_DLY_EN_READ 0x00010000ul |
UWB 2 RX_CAL register settings.
Specified RX_CAL register settings of UWB 2 Click driver.
| #define UWB2_RX_CAL_COMP_DLY_MASK 0x000F0000ul |
| #define UWB2_RX_CAL_COMP_DLY_OPTIMAL 0x00020000ul |
| #define UWB2_RX_CAL_RESI_CALIBRATION_FAILED 0x1FFFFFFFul |
UWB 2 RX_CAL_RESI register settings.
Specified RX_CAL_RESI register settings of UWB 2 Click driver.
| #define UWB2_RX_CAL_RESQ_CALIBRATION_FAILED 0x1FFFFFFFul |
UWB 2 RX_CAL_RESQ register settings.
Specified RX_CAL_RESQ register settings of UWB 2 Click driver.
| #define UWB2_RX_CAL_STS_CALIBRATION_DONE 0x01 |
UWB 2 RX_CAL_STS register settings.
Specified RX_CAL_STS register settings of UWB 2 Click driver.
| #define UWB2_RX_CODE_24 0x18 |
| #define UWB2_RX_CODE_9 0x09 |
| #define UWB2_RX_CODE_MAX 0x1D |
| #define UWB2_RX_CODE_MIN 0x01 |
| #define UWB2_RX_FINFO_RNG_MASK 0x00008000ul |
| #define UWB2_RX_FINFO_RXBR_MASK 0x00002000ul |
| #define UWB2_RX_FINFO_RXFLEN_MASK 0x000003FFul |
| #define UWB2_RX_FINFO_RXNSPL_MASK 0x00001800ul |
| #define UWB2_RX_FINFO_RXPACC_MASK 0xFFF00000ul |
UWB 2 RX_FINFO register settings.
Specified RX_FINFO register settings of UWB 2 Click driver.
| #define UWB2_RX_FINFO_RXPRF_MASK 0x00030000ul |
| #define UWB2_RX_FINFO_RXPSR_MASK 0x000C0000ul |
| #define UWB2_RX_SFD_TOC_DEFAULT 0x0081u |
UWB 2 RX_SFD_TOC register settings.
Specified RX_SFD_TOC register settings of UWB 2 Click driver.
| #define UWB2_RX_TUNE_DGC_CFG_0 0x10000240ul |
| #define UWB2_RX_TUNE_DGC_CFG_1 0x1B6DA489ul |
| #define UWB2_RX_TUNE_DGC_CFG_RESERVED_BITS 0x80F4u |
| #define UWB2_RX_TUNE_DGC_CFG_RX_TUNE_EN_MASK 0x0001u |
| #define UWB2_RX_TUNE_DGC_CFG_THR_64_MASK 0x7E00u |
| #define UWB2_RX_TUNE_DGC_CFG_THR_64_OPTIMISED 0x6400u |
UWB 2 RX_TUNE register settings.
Specified RX_TUNE register settings of UWB 2 Click driver.
| #define UWB2_RX_TUNE_DGC_LUT_0_CH5 0x0001C0FDul |
| #define UWB2_RX_TUNE_DGC_LUT_0_CH9 0x0002A8FEul |
| #define UWB2_RX_TUNE_DGC_LUT_1_CH5 0x0001C43Eul |
| #define UWB2_RX_TUNE_DGC_LUT_1_CH9 0x0002AC36ul |
| #define UWB2_RX_TUNE_DGC_LUT_2_CH5 0x0001C6BEul |
| #define UWB2_RX_TUNE_DGC_LUT_2_CH9 0x0002A5FEul |
| #define UWB2_RX_TUNE_DGC_LUT_3_CH5 0x0001C77Eul |
| #define UWB2_RX_TUNE_DGC_LUT_3_CH9 0x0002AF3Eul |
| #define UWB2_RX_TUNE_DGC_LUT_4_CH5 0x0001C736ul |
| #define UWB2_RX_TUNE_DGC_LUT_4_CH9 0x0002AF7Dul |
| #define UWB2_RX_TUNE_DGC_LUT_5_CH5 0x0001CFB5ul |
| #define UWB2_RX_TUNE_DGC_LUT_5_CH9 0x0002AFB5ul |
| #define UWB2_RX_TUNE_DGC_LUT_6_CH5 0x0001CFF5ul |
| #define UWB2_RX_TUNE_DGC_LUT_6_CH9 0x0002AFB5ul |
| #define UWB2_RX_TX_LEDS_DISABLE 0 |
UWB 2 RX TX LEDs settings.
Specified RX TX LEDs settings of UWB 2 Click driver.
| #define UWB2_RX_TX_LEDS_ENABLE 1 |
| #define UWB2_SEQ_CTRL_AINIT2IDLE_MASK 0x00000100ul |
| #define UWB2_SEQ_CTRL_ARXSLP_MASK 0x00001000ul |
| #define UWB2_SEQ_CTRL_ATXSLP_MASK 0x00000800ul |
| #define UWB2_SEQ_CTRL_CIARUNE_MASK 0x00020000ul |
| #define UWB2_SEQ_CTRL_FORCE2INIT_MASK 0x00800000ul |
| #define UWB2_SEQ_CTRL_LP_CLK_DIV_MASK 0xFC000000ul |
UWB 2 SEQ_CTRL register settings.
Specified SEQ_CTRL register settings of UWB 2 Click driver.
| #define UWB2_SEQ_CTRL_PLL_SYNC_MASK 0x00008000ul |
| #define UWB2_SEQ_CTRL_RESERVED_BITS 0x00010638ul |
| #define UWB2_SET_DATA_SAMPLE_EDGE SET_SPI_DATA_SAMPLE_EDGE |
Data sample selection.
This macro sets data samples for SPI modules.
| #define UWB2_SET_DATA_SAMPLE_MIDDLE SET_SPI_DATA_SAMPLE_MIDDLE |
| #define UWB2_SFD_TYPE_DW_16 0x02 |
| #define UWB2_SFD_TYPE_DW_8 0x01 |
| #define UWB2_SFD_TYPE_IEEE_4A 0x00 |
| #define UWB2_SFD_TYPE_IEEE_4Z 0x03 |
| #define UWB2_SPI_16BIT_ADDR 0x4000u |
| #define UWB2_SPI_BASE_ADDR_MASK 0x3E00u |
| #define UWB2_SPI_FAST_CMD 0x0100u |
| #define UWB2_SPI_MASKED_WRITE_16BIT 0x0002u |
| #define UWB2_SPI_MASKED_WRITE_32BIT 0x0003u |
| #define UWB2_SPI_MASKED_WRITE_8BIT 0x0001u |
| #define UWB2_SPI_MODE_MASK 0x0003u |
| #define UWB2_SPI_SUB_ADDR_MASK 0x01FCu |
| #define UWB2_SPI_WRITE 0x8000u |
UWB 2 spi command frame setting.
Specified spi command frame setting of UWB 2 Click driver.
| #define UWB2_STS_CFG_CPS_LEN_64 0x0007u |
UWB 2 STS_CFG register settings.
Specified STS_CFG register settings of UWB 2 Click driver.
| #define UWB2_STS_CFG_CPS_LEN_MASK 0x00FFu |
| #define UWB2_STS_CFG_RESERVED_BITS 0x1000u |
| #define UWB2_STS_CONF_1_FP_AGREED_EN_MASK 0x10000000ul |
| #define UWB2_STS_CONF_1_RES_B0_DEFAULT 0x00000094ul |
| #define UWB2_STS_CONF_1_RES_B0_MASK 0x000000FFul |
| #define UWB2_STS_CONF_1_RESERVED_BITS 0x003EED00ul |
| #define UWB2_STS_CONF_1_STS_CQ_EN_MASK 0x20000000ul |
| #define UWB2_STS_CONF_1_STS_PGR_EN_MASK 0x80000000ul |
UWB 2 STS_CONF_1 register settings.
Specified STS_CONF_1 register settings of UWB 2 Click driver.
| #define UWB2_STS_CONF_1_STS_SS_EN_MASK 0x40000000ul |
| #define UWB2_SYS_CFG_AUTO_ACK_MASK 0x00000800ul |
| #define UWB2_SYS_CFG_CIA_IPATOV_MASK 0x00000080ul |
| #define UWB2_SYS_CFG_CIA_STS_MASK 0x00000100ul |
| #define UWB2_SYS_CFG_CP_SDC_SPC_MASK 0x0000B000ul |
| #define UWB2_SYS_CFG_DIS_DRXB_MASK 0x00000008ul |
| #define UWB2_SYS_CFG_DIS_FCE_MASK 0x00000004ul |
| #define UWB2_SYS_CFG_DIS_FCS_TX_MASK 0x00000002ul |
| #define UWB2_SYS_CFG_FAST_AAT_MASK 0x00040000ul |
UWB 2 SYS_CFG register settings.
Specified SYS_CFG register settings of UWB 2 Click driver.
| #define UWB2_SYS_CFG_FFEN_MASK 0x00000001ul |
| #define UWB2_SYS_CFG_PDOA_MODE_MASK 0x00030000ul |
| #define UWB2_SYS_CFG_PHR_6M8_MASK 0x00000020ul |
| #define UWB2_SYS_CFG_PHR_MODE_MASK 0x00000010ul |
| #define UWB2_SYS_CFG_RXAUTR_MASK 0x00000400ul |
| #define UWB2_SYS_CFG_RXWTOE_MASK 0x00000200ul |
| #define UWB2_SYS_CFG_SPI_CRCEN_MASK 0x00000040ul |
| #define UWB2_SYS_ENABLE_LO_AAT_EN_MASK 0x00000008ul |
| #define UWB2_SYS_ENABLE_LO_ARFE_EN_MASK 0x20000000ul |
UWB 2 SYS_ENABLE_LO register settings.
Specified SYS_ENABLE_LO register settings of UWB 2 Click driver.
| #define UWB2_SYS_ENABLE_LO_CIADONE_EN_MASK 0x00000400ul |
| #define UWB2_SYS_ENABLE_LO_CIAERR_EN_MASK 0x00040000ul |
| #define UWB2_SYS_ENABLE_LO_CPERR_EN_MASK 0x10000000ul |
| #define UWB2_SYS_ENABLE_LO_CPLOCK_EN_MASK 0x00000002ul |
| #define UWB2_SYS_ENABLE_LO_HPDWARN_EN_MASK 0x08000000ul |
| #define UWB2_SYS_ENABLE_LO_PLLHILO_EN_MASK 0x02000000ul |
| #define UWB2_SYS_ENABLE_LO_RCINIT_EN_MASK 0x01000000ul |
| #define UWB2_SYS_ENABLE_LO_RXFCE_EN_MASK 0x00008000ul |
| #define UWB2_SYS_ENABLE_LO_RXFCG_EN_MASK 0x00004000ul |
| #define UWB2_SYS_ENABLE_LO_RXFR_EN_MASK 0x00002000ul |
| #define UWB2_SYS_ENABLE_LO_RXFSL_EN_MASK 0x00010000ul |
| #define UWB2_SYS_ENABLE_LO_RXFTO_EN_MASK 0x00020000ul |
| #define UWB2_SYS_ENABLE_LO_RXOVRR_EN_MASK 0x00100000ul |
| #define UWB2_SYS_ENABLE_LO_RXPHD_EN_MASK 0x00000800ul |
| #define UWB2_SYS_ENABLE_LO_RXPHE_EN_MASK 0x00001000ul |
| #define UWB2_SYS_ENABLE_LO_RXPRD_EN_MASK 0x00000100ul |
| #define UWB2_SYS_ENABLE_LO_RXPTO_EN_MASK 0x00200000ul |
| #define UWB2_SYS_ENABLE_LO_RXSFDD_EN_MASK 0x00000200ul |
| #define UWB2_SYS_ENABLE_LO_RXSTO_EN_MASK 0x04000000ul |
| #define UWB2_SYS_ENABLE_LO_SPICRCE_EN_MASK 0x00000004ul |
| #define UWB2_SYS_ENABLE_LO_SPIRDY_EN_MASK 0x00800000ul |
| #define UWB2_SYS_ENABLE_LO_TXFRB_EN_MASK 0x00000010ul |
| #define UWB2_SYS_ENABLE_LO_TXFRS_EN_MASK 0x00000080ul |
| #define UWB2_SYS_ENABLE_LO_TXPHS_EN_MASK 0x00000040ul |
| #define UWB2_SYS_ENABLE_LO_TXPRS_EN_MASK 0x00000020ul |
| #define UWB2_SYS_ENABLE_LO_VWARN_EN_MASK 0x00080000ul |
| #define UWB2_SYS_STATE_PMSC_STATE_IDLE 0x00030000ul |
| #define UWB2_SYS_STATE_PMSC_STATE_IDLE_RC 0x00010000ul |
| #define UWB2_SYS_STATE_PMSC_STATE_MASK 0x001F0000ul |
| #define UWB2_SYS_STATE_PMSC_STATE_RX 0x00120000ul |
| #define UWB2_SYS_STATE_PMSC_STATE_TX 0x00080000ul |
| #define UWB2_SYS_STATE_PMSC_STATE_WAKEUP 0x00000000ul |
UWB 2 SYS_STATE register settings.
Specified SYS_STATE register settings of UWB 2 Click driver.
| #define UWB2_SYS_STATE_RX_STATE_CNFG_DATA_RX 0x00000D00ul |
| #define UWB2_SYS_STATE_RX_STATE_CNFG_PHR_RX 0x00000800ul |
| #define UWB2_SYS_STATE_RX_STATE_DATA_RATE_RDY 0x00000A00ul |
| #define UWB2_SYS_STATE_RX_STATE_DATA_RX_SEQ 0x00000C00ul |
| #define UWB2_SYS_STATE_RX_STATE_IDLE 0x00000000ul |
| #define UWB2_SYS_STATE_RX_STATE_LAST_SYMBOL 0x00000F00ul |
| #define UWB2_SYS_STATE_RX_STATE_MASK 0x00003F00ul |
| #define UWB2_SYS_STATE_RX_STATE_PHR_NOT_OK 0x00000E00ul |
| #define UWB2_SYS_STATE_RX_STATE_PHR_RX_STRT 0x00000900ul |
| #define UWB2_SYS_STATE_RX_STATE_PREAMBLE_FND 0x00000500ul |
| #define UWB2_SYS_STATE_RX_STATE_PREAMBLE_TO 0x00000600ul |
| #define UWB2_SYS_STATE_RX_STATE_RSP_NOT_OK 0x00001200ul |
| #define UWB2_SYS_STATE_RX_STATE_RSP_OK 0x00001100ul |
| #define UWB2_SYS_STATE_RX_STATE_RX_RDY 0x00000400ul |
| #define UWB2_SYS_STATE_RX_STATE_SFD_FND 0x00000700ul |
| #define UWB2_SYS_STATE_RX_STATE_START_ANALOG 0x00000100ul |
| #define UWB2_SYS_STATE_RX_STATE_WAIT_RSD_DONE 0x00001000ul |
| #define UWB2_SYS_STATE_TX_STATE_DATA 0x00000005ul |
| #define UWB2_SYS_STATE_TX_STATE_IDLE 0x00000000ul |
| #define UWB2_SYS_STATE_TX_STATE_MASK 0x0000000Ful |
| #define UWB2_SYS_STATE_TX_STATE_PHR 0x00000003ul |
| #define UWB2_SYS_STATE_TX_STATE_PREAMBLE 0x00000001ul |
| #define UWB2_SYS_STATE_TX_STATE_SDE 0x00000004ul |
| #define UWB2_SYS_STATE_TX_STATE_SFD 0x00000002ul |
| #define UWB2_SYS_STATUS_HI_AER_ERR_MASK 0x0080u |
| #define UWB2_SYS_STATUS_HI_AES_DONE_MASK 0x0040u |
| #define UWB2_SYS_STATUS_HI_CCA_FAIL_MASK 0x1000u |
UWB 2 SYS_STATUS_HI register settings.
Specified SYS_STATUS_HI register settings of UWB 2 Click driver.
| #define UWB2_SYS_STATUS_HI_CMD_ERR_MASK 0x0100u |
| #define UWB2_SYS_STATUS_HI_GPIOIRQ_MASK 0x0020u |
| #define UWB2_SYS_STATUS_HI_RXPREJ_MASK 0x0002u |
| #define UWB2_SYS_STATUS_HI_SPI_OVF_MASK 0x0200u |
| #define UWB2_SYS_STATUS_HI_SPI_UNF_MASK 0x0400u |
| #define UWB2_SYS_STATUS_HI_SPIERR_MASK 0x0800u |
| #define UWB2_SYS_STATUS_HI_VT_DET_MASK 0x0010u |
| #define UWB2_SYS_STATUS_LO_AAT_MASK 0x00000008ul |
| #define UWB2_SYS_STATUS_LO_ARFE_MASK 0x20000000ul |
UWB 2 SYS_STATUS_LO register settings.
Specified SYS_STATUS_LO register settings of UWB 2 Click driver.
| #define UWB2_SYS_STATUS_LO_CIADONE_MASK 0x00000400ul |
| #define UWB2_SYS_STATUS_LO_CIAERR_MASK 0x00040000ul |
| #define UWB2_SYS_STATUS_LO_CPERR_MASK 0x10000000ul |
| #define UWB2_SYS_STATUS_LO_CPLOCK_MASK 0x00000002ul |
| #define UWB2_SYS_STATUS_LO_HPDWARN_MASK 0x08000000ul |
| #define UWB2_SYS_STATUS_LO_IRQS_MASK 0x00000001ul |
| #define UWB2_SYS_STATUS_LO_PLLHILO_MASK 0x02000000ul |
| #define UWB2_SYS_STATUS_LO_RCINIT_MASK 0x01000000ul |
| #define UWB2_SYS_STATUS_LO_RXFCE_MASK 0x00008000ul |
| #define UWB2_SYS_STATUS_LO_RXFCG_MASK 0x00004000ul |
| #define UWB2_SYS_STATUS_LO_RXFR_MASK 0x00002000ul |
| #define UWB2_SYS_STATUS_LO_RXFSL_MASK 0x00010000ul |
| #define UWB2_SYS_STATUS_LO_RXFTO_MASK 0x00020000ul |
| #define UWB2_SYS_STATUS_LO_RXOVRR_MASK 0x00100000ul |
| #define UWB2_SYS_STATUS_LO_RXPHD_MASK 0x00000800ul |
| #define UWB2_SYS_STATUS_LO_RXPHE_MASK 0x00001000ul |
| #define UWB2_SYS_STATUS_LO_RXPRD_MASK 0x00000100ul |
| #define UWB2_SYS_STATUS_LO_RXPTO_MASK 0x00200000ul |
| #define UWB2_SYS_STATUS_LO_RXSFDD_MASK 0x00000200ul |
| #define UWB2_SYS_STATUS_LO_RXSTO_MASK 0x04000000ul |
| #define UWB2_SYS_STATUS_LO_SPICRCE_MASK 0x00000004ul |
| #define UWB2_SYS_STATUS_LO_SPIRDY_MASK 0x00800000ul |
| #define UWB2_SYS_STATUS_LO_TXFRB_MASK 0x00000010ul |
| #define UWB2_SYS_STATUS_LO_TXFRS_MASK 0x00000080ul |
| #define UWB2_SYS_STATUS_LO_TXPHS_MASK 0x00000040ul |
| #define UWB2_SYS_STATUS_LO_TXPRS_MASK 0x00000020ul |
| #define UWB2_SYS_STATUS_LO_VWARN_MASK 0x00080000ul |
| #define UWB2_TX_CODE_24 0x18 |
| #define UWB2_TX_CODE_9 0x09 |
| #define UWB2_TX_CODE_MAX 0x1D |
| #define UWB2_TX_CODE_MIN 0x01 |
| #define UWB2_TX_FCTRL_HI_FINE_PLEN_MASK 0xFF00u |
UWB 2 TX_FCTRL_HI register settings.
Specified TX_FCTRL_HI register settings of UWB 2 Click driver.
| #define UWB2_TX_FCTRL_LO_TR_MASK 0x00000800ul |
| #define UWB2_TX_FCTRL_LO_TX_BR_MASK 0x00000400ul |
| #define UWB2_TX_FCTRL_LO_TXB_OFFSET_MASK 0x03FF0000ul |
UWB 2 TX_FCTRL_LO register settings.
Specified TX_FCTRL_LO register settings of UWB 2 Click driver.
| #define UWB2_TX_FCTRL_LO_TXFLEN_MASK 0x000003FFul |
| #define UWB2_TX_FCTRL_LO_TXPSR_MASK 0x0000F000ul |
| #define UWB2_TX_PLEN_1024 0x02 |
| #define UWB2_TX_PLEN_128 0x05 |
| #define UWB2_TX_PLEN_1536 0x06 |
| #define UWB2_TX_PLEN_2048 0x0A |
| #define UWB2_TX_PLEN_256 0x09 |
| #define UWB2_TX_PLEN_32 0x04 |
| #define UWB2_TX_PLEN_4096 0x03 |
| #define UWB2_TX_PLEN_512 0x0D |
| #define UWB2_TX_PLEN_64 0x01 |
| #define UWB2_WAIT_TIMEOUT_MS 5000u |
UWB 2 wait status timeout setting.
Specified wait status timeout setting of UWB 2 Click driver.
| #define UWB2_XTAL_TRIM_DEFAULT 0x2E |
UWB 2 XTAL register settings.
Specified XTAL register settings of UWB 2 Click driver.
| #define UWB2_XTAL_TRIM_MASK 0x3F |