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#define | VCPMONITOR2_MAP_MIKROBUS(cfg, mikrobus) |
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#define | VCPMONITOR2_RETVAL uint8_t |
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#define | VCPMONITOR2_OK 0x00 |
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#define | VCPMONITOR2_INIT_ERROR 0xFF |
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#define | VCPMONITOR2_DEVICE_SLAVE_ADDR_GND 0x40 |
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#define | VCPMONITOR2_DEVICE_SLAVE_ADDR_VCC 0x41 |
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#define | VCPMONITOR2_DEVICE_SLAVE_ADDR_SCL 0x42 |
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#define | VCPMONITOR2_DEVICE_SLAVE_ADDR_SDA 0x43 |
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#define | VCPMONITOR2_STATUS_ADDR_GND_GND 0x70 |
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#define | VCPMONITOR2_STATUS_ADDR_VCC_GND 0x72 |
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#define | VCPMONITOR2_STATUS_ADDR_GND_VCC 0x71 |
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#define | VCPMONITOR2_STATUS_ADDR_VCC_VCC 0x73 |
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#define | VCPMONITOR2_ALERT_REG_INPUT 0x00 |
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#define | VCPMONITOR2_ALERT_REG_POLARITY 0x02 |
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#define | VCPMONITOR2_ALERT_REG_CONFIG 0x03 |
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#define | VCPMONITOR2_REG_CONFIGURATION 0x00 |
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#define | VCPMONITOR2_REG_CH_1_SHUNT_VOLT 0x01 |
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#define | VCPMONITOR2_REG_CH_1_BUS_VOLT 0x02 |
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#define | VCPMONITOR2_REG_CH_2_SHUNT_VOLT 0x03 |
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#define | VCPMONITOR2_REG_CH_2_BUS_VOLT 0x04 |
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#define | VCPMONITOR2_REG_CH_3_SHUNT_VOLT 0x05 |
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#define | VCPMONITOR2_REG_CH_3_BUS_VOLT 0x06 |
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#define | VCPMONITOR2_REG_CH_1_CRITICAL_ALT 0x07 |
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#define | VCPMONITOR2_REG_CH_1_WARNING_ALT 0x08 |
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#define | VCPMONITOR2_REG_CH_2_CRITICAL_ALT 0x09 |
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#define | VCPMONITOR2_REG_CH_2_WARNING_ALT 0x0A |
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#define | VCPMONITOR2_REG_CH_3_CRITICAL_ALT 0x0B |
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#define | VCPMONITOR2_REG_CH_3_WARNING_ALT 0x0C |
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#define | VCPMONITOR2_REG_SHUNT_VOLT_SUM 0x0D |
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#define | VCPMONITOR2_REG_SHUNT_VOLT_SUM_LIMIT 0x0E |
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#define | VCPMONITOR2_REG_MASK_ENABLE 0x0F |
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#define | VCPMONITOR2_REG_PWR_UPPER_LIMIT 0x10 |
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#define | VCPMONITOR2_REG_PWR_LOWER_LIMIT 0x11 |
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#define | VCPMONITOR2_REG_MANUFACTURER_ID 0xFE |
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#define | VCPMONITOR2_REG_DIE_ID 0xFF |
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#define | VCPMONITOR2_DEF_MANUFACTURE_ID 0x5449 |
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#define | VCPMONITOR2_DEF_DIE_ID 0x3220 |
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#define | VCPMONITOR2_DEF_PWR_LOWER_LIMIT 0x2328 |
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#define | VCPMONITOR2_DEF_PWR_UPPER_LIMIT 0x2F10 |
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#define | VCPMONITOR2_DEF_MASK_ENABLE 0x0002 |
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#define | VCPMONITOR2_DEF_SHUNT_VOLT_SUM_LIMIT 0x7FFE |
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#define | VCPMONITOR2_DEF_CONFIGURATION 0x7127 |
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#define | VCPMONITOR2_DEF_CH_1234_ALERT 0x7FF8 |
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#define | VCPMONITOR2_CFG_SW_RESET 0x8000 |
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#define | VCPMONITOR2_CFG_CH_1_ENABLE 0x4000 |
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#define | VCPMONITOR2_CFG_CH_1_DISABLE 0x0000 |
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#define | VCPMONITOR2_CFG_CH_2_ENABLE 0x2000 |
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#define | VCPMONITOR2_CFG_CH_2_DISABLE 0x0000 |
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#define | VCPMONITOR2_CFG_CH_3_ENABLE 0x1000 |
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#define | VCPMONITOR2_CFG_CH_3_DISABLE 0x0000 |
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#define | VCPMONITOR2_CFG_AVG_1 0x0000 |
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#define | VCPMONITOR2_CFG_AVG_4 0x0200 |
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#define | VCPMONITOR2_CFG_AVG_16 0x0400 |
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#define | VCPMONITOR2_CFG_AVG_64 0x0600 |
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#define | VCPMONITOR2_CFG_AVG_128 0x0800 |
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#define | VCPMONITOR2_CFG_AVG_256 0x0A00 |
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#define | VCPMONITOR2_CFG_AVG_512 0x0C00 |
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#define | VCPMONITOR2_CFG_AVG_1024 0x0D00 |
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#define | VCPMONITOR2_CFG_VBUS_CT_140us 0x0000 |
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#define | VCPMONITOR2_CFG_VBUS_CT_204us 0x0040 |
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#define | VCPMONITOR2_CFG_VBUS_CT_332us 0x0080 |
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#define | VCPMONITOR2_CFG_VBUS_CT_588us 0x00C0 |
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#define | VCPMONITOR2_CFG_VBUS_CT_1100us 0x0100 |
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#define | VCPMONITOR2_CFG_VBUS_CT_2116us 0x0140 |
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#define | VCPMONITOR2_CFG_VBUS_CT_4156us 0x0180 |
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#define | VCPMONITOR2_CFG_VBUS_CT_8244us 0x01C0 |
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#define | VCPMONITOR2_CFG_VSH_CT_140us 0x0000 |
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#define | VCPMONITOR2_CFG_VSH_CT_204us 0x0008 |
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#define | VCPMONITOR2_CFG_VSH_CT_332us 0x0010 |
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#define | VCPMONITOR2_CFG_VSH_CT_588us 0x0018 |
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#define | VCPMONITOR2_CFG_VSH_CT_1100us 0x0020 |
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#define | VCPMONITOR2_CFG_VSH_CT_2116us 0x0028 |
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#define | VCPMONITOR2_CFG_VSH_CT_4156us 0x0030 |
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#define | VCPMONITOR2_CFG_VSH_CT_8244us 0x0038 |
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#define | VCPMONITOR2_CFG_MODE_POWER_DOWN 0x0000 |
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#define | VCPMONITOR2_CFG_MODE_SS_SHUNT_VOLT 0x0001 |
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#define | VCPMONITOR2_CFG_MODE_SS_BUS_VOLT 0x0002 |
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#define | VCPMONITOR2_CFG_MODE_SS_SHUNT_BUS_VOLT 0x0003 |
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#define | VCPMONITOR2_CFG_MODE_CONT_SHUNT_VOLT 0x0005 |
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#define | VCPMONITOR2_CFG_MODE_CONT_BUS_VOLT 0x0006 |
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#define | VCPMONITOR2_CFG_MODE_CONT_SHUNT_BUS_VOLT 0x0007 |
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#define | VCPMONITOR2_CFG_MASK_SCC_1_ENABLE 0x4000 |
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#define | VCPMONITOR2_CFG_MASK_SCC_2_ENABLE 0x2000 |
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#define | VCPMONITOR2_CFG_MASK_SCC_3_ENABLE 0x1000 |
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#define | VCPMONITOR2_CFG_MASK_SCC_1_DISABLE 0x0000 |
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#define | VCPMONITOR2_CFG_MASK_SCC_2_DISABLE 0x0000 |
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#define | VCPMONITOR2_CFG_MASK_SCC_3_DISABLE 0x0000 |
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#define | VCPMONITOR2_CFG_MASK_WEN_TRANSPARENT 0x0000 |
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#define | VCPMONITOR2_CFG_MASK_WEN_LATCH_ENABLED 0x0800 |
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#define | VCPMONITOR2_CFG_MASK_CEN_TRANSPARENT 0x0000 |
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#define | VCPMONITOR2_CFG_MASK_CEN_LATCH_ENABLED 0x0400 |
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#define | VCPMONITOR2_CFG_MASK_CF_1_ENABLE 0x0080 |
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#define | VCPMONITOR2_CFG_MASK_CF_2_ENABLE 0x0100 |
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#define | VCPMONITOR2_CFG_MASK_CF_3_ENABLE 0x0200 |
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#define | VCPMONITOR2_CFG_MASK_CF_1_DISABLE 0x0000 |
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#define | VCPMONITOR2_CFG_MASK_CF_2_DISABLE 0x0000 |
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#define | VCPMONITOR2_CFG_MASK_CF_3_DISABLE 0x0000 |
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#define | VCPMONITOR2_CFG_MASK_SF_ENABLE 0x0040 |
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#define | VCPMONITOR2_CFG_MASK_SF_DISABLE 0x0000 |
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#define | VCPMONITOR2_CFG_MASK_VF_1_ENABLE 0x0008 |
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#define | VCPMONITOR2_CFG_MASK_VF_2_ENABLE 0x0010 |
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#define | VCPMONITOR2_CFG_MASK_VF_3_ENABLE 0x0020 |
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#define | VCPMONITOR2_CFG_MASK_VF_1_DISABLE 0x0000 |
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#define | VCPMONITOR2_CFG_MASK_VF_2_DISABLE 0x0000 |
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#define | VCPMONITOR2_CFG_MASK_VF_3_DISABLE 0x0000 |
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#define | VCPMONITOR2_CFG_MASK_PVF_ENABLE 0x0004 |
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#define | VCPMONITOR2_CFG_MASK_TCF_ENABLE 0x0002 |
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#define | VCPMONITOR2_CFG_MASK_CVRF_ENABLE 0x0001 |
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#define | VCPMONITOR2_CFG_MASK_PVF_DISABLE 0x0000 |
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#define | VCPMONITOR2_CFG_MASK_TCF_DISABLE 0x0000 |
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#define | VCPMONITOR2_CFG_MASK_CVRF_DISABLE 0x0000 |
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#define | VCPMONITOR2_CHANNEL_1 0x01 |
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#define | VCPMONITOR2_CHANNEL_2 0x02 |
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#define | VCPMONITOR2_CHANNEL_3 0x03 |
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#define | VCPMONITOR2_ALERT_PVALID 0x01 |
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#define | VCPMONITOR2_ALERT_WRNG 0x02 |
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#define | VCPMONITOR2_ALERT_CRTCL 0x04 |
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#define | VCPMONITOR2_ALERT_TCTRL 0x08 |
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#define | DEVICE_OK 0 |
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#define | DEVICE_ERROR 1 |
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