Waveform 3 Registers List

List of registers of Waveform 3 Click driver. More...

Macros
#define	WAVEFORM3_REG_B28_BIT   1 << 13
	Waveform 3 B28 register bit.
#define	WAVEFORM3_REG_HLB_BIT   1 << 12
	Waveform 3 HLB register bit.
#define	WAVEFORM3_REG_FSEL_BIT   1 << 11
	Waveform 3 FSEL register bit.
#define	WAVEFORM3_REG_PSEL_BIT   1 << 10
	Waveform 3 PSEL register bit.
#define	WAVEFORM3_REG_RESET_BIT   1 << 8
	Waveform 3 RESET register bit.
#define	WAVEFORM3_REG_SLEEP1_BIT   1 << 7
	Waveform 3 SLEEP1 register bit.
#define	WAVEFORM3_REG_SLEEP12_BIT   1 << 6
	Waveform 3 SLEEP12 register bit.
#define	WAVEFORM3_REG_OPBITEN_BIT   1 << 5
	Waveform 3 OPBITEN register bit.
#define	WAVEFORM3_REG_DIV2_BIT   1 << 3
	Waveform 3 DIV2 register bit.
#define	WAVEFORM3_REG_MODE_BIT   1 << 1
	Waveform 3 MODE register bit.
#define	WAVEFORM3_REG_RESET_CLEAR   0x0000
	Waveform 3 RESET register bit.

Detailed Description

List of registers of Waveform 3 Click driver.

Macro Definition Documentation

WAVEFORM3_REG_B28_BIT

#define WAVEFORM3_REG_B28_BIT   1 << 13

Waveform 3 B28 register bit.

Allows 28-bit frequency register to operate as two 14-bit registers of Waveform 3 Click driver.

WAVEFORM3_REG_DIV2_BIT

#define WAVEFORM3_REG_DIV2_BIT   1 << 3

Waveform 3 DIV2 register bit.

This bit causes the MSB of the DAC data to be output at the VOUT pin.

WAVEFORM3_REG_FSEL_BIT

#define WAVEFORM3_REG_FSEL_BIT   1 << 11

Waveform 3 FSEL register bit.

This bit defines whether the FREQ0 register or the FREQ1 register is used in the phase accumulator.

WAVEFORM3_REG_HLB_BIT

#define WAVEFORM3_REG_HLB_BIT   1 << 12

Waveform 3 HLB register bit.

This control bit allows the user to continuously load the MSBs or LSBs of a frequency register while ignoring the remaining 14 bits.

WAVEFORM3_REG_MODE_BIT

#define WAVEFORM3_REG_MODE_BIT   1 << 1

Waveform 3 MODE register bit.

This bit bypasses the SIN ROM, resulting in a triangle output from the DAC.

WAVEFORM3_REG_OPBITEN_BIT

#define WAVEFORM3_REG_OPBITEN_BIT   1 << 5

Waveform 3 OPBITEN register bit.

This bit, in association with the MODE bit, controls the output at the VOUT pin.

WAVEFORM3_REG_PSEL_BIT

#define WAVEFORM3_REG_PSEL_BIT   1 << 10

Waveform 3 PSEL register bit.

This bit defines whether the PHASE0 register data or the PHASE1 register data is added to the output of the phase accumulator.

WAVEFORM3_REG_RESET_BIT

#define WAVEFORM3_REG_RESET_BIT   1 << 8

Waveform 3 RESET register bit.

This bit resets internal registers to 0.

WAVEFORM3_REG_RESET_CLEAR

#define WAVEFORM3_REG_RESET_CLEAR   0x0000

Waveform 3 RESET register bit.

This bit disables the reset function.

WAVEFORM3_REG_SLEEP12_BIT

#define WAVEFORM3_REG_SLEEP12_BIT   1 << 6

Waveform 3 SLEEP12 register bit.

This bit powers down the on-chip DAC. This is useful when the AD9837 is used to output the MSB of the DAC data.

WAVEFORM3_REG_SLEEP1_BIT

#define WAVEFORM3_REG_SLEEP1_BIT   1 << 7

Waveform 3 SLEEP1 register bit.

This bit disables the internal MCLK. The DAC output remains at its present value because the NCO is no longer accumulating.