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#define | WAVEFORM4_REG_SPI_CONFIG 0x0000 |
| Waveform 4 register map.
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#define | WAVEFORM4_REG_POWER_CONFIG 0x0001 |
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#define | WAVEFORM4_REG_CLOCK_CONFIG 0x0002 |
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#define | WAVEFORM4_REG_REF_ADJ 0x0003 |
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#define | WAVEFORM4_REG_DAC4_AGAIN 0x0004 |
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#define | WAVEFORM4_REG_DAC3_AGAIN 0x0005 |
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#define | WAVEFORM4_REG_DAC2_AGAIN 0x0006 |
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#define | WAVEFORM4_REG_DAC1_AGAIN 0x0007 |
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#define | WAVEFORM4_REG_DACX_RANGE 0x0008 |
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#define | WAVEFORM4_REG_DAC4_RSET 0x0009 |
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#define | WAVEFORM4_REG_DAC3_RSET 0x000A |
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#define | WAVEFORM4_REG_DAC2_RSET 0x000B |
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#define | WAVEFORM4_REG_DAC1_RSET 0x000C |
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#define | WAVEFORM4_REG_CAL_CONFIG 0x000D |
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#define | WAVEFORM4_REG_COMP_OFFSET 0x000E |
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#define | WAVEFORM4_REG_RAM_UPDATE 0x001D |
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#define | WAVEFORM4_REG_PAT_STATUS 0x001E |
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#define | WAVEFORM4_REG_PAT_TYPE 0x001F |
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#define | WAVEFORM4_REG_PATTERN_DLY 0x0020 |
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#define | WAVEFORM4_REG_DAC4_DOF 0x0022 |
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#define | WAVEFORM4_REG_DAC3_DOF 0x0023 |
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#define | WAVEFORM4_REG_DAC2_DOF 0x0024 |
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#define | WAVEFORM4_REG_DAC1_DOF 0x0025 |
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#define | WAVEFORM4_REG_WAV43_CONFIG 0x0026 |
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#define | WAVEFORM4_REG_WAV21_CONFIG 0x0027 |
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#define | WAVEFORM4_REG_PAT_TIMEBASE 0x0028 |
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#define | WAVEFORM4_REG_PAT_PERIOD 0x0029 |
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#define | WAVEFORM4_REG_DAC43_PATX 0x002A |
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#define | WAVEFORM4_REG_DAC21_PATX 0x002B |
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#define | WAVEFORM4_REG_DOUT_START_DLY 0x002C |
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#define | WAVEFORM4_REG_DOUT_CONFIG 0x002D |
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#define | WAVEFORM4_REG_DAC4_CST 0x002E |
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#define | WAVEFORM4_REG_DAC3_CST 0x002F |
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#define | WAVEFORM4_REG_DAC2_CST 0x0030 |
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#define | WAVEFORM4_REG_DAC1_CST 0x0031 |
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#define | WAVEFORM4_REG_DAC4_DGAIN 0x0032 |
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#define | WAVEFORM4_REG_DAC3_DGAIN 0x0033 |
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#define | WAVEFORM4_REG_DAC2_DGAIN 0x0034 |
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#define | WAVEFORM4_REG_DAC1_DGAIN 0x0035 |
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#define | WAVEFORM4_REG_SAW43_CONFIG 0x0036 |
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#define | WAVEFORM4_REG_SAW21_CONFIG 0x0037 |
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#define | WAVEFORM4_REG_DDS_TW32 0x003E |
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#define | WAVEFORM4_REG_DDS_TW1 0x003F |
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#define | WAVEFORM4_REG_DDS4_PW 0x0040 |
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#define | WAVEFORM4_REG_DDS3_PW 0x0041 |
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#define | WAVEFORM4_REG_DDS2_PW 0x0042 |
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#define | WAVEFORM4_REG_DDS1_PW 0x0043 |
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#define | WAVEFORM4_REG_TRIG_TW_SEL 0x0044 |
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#define | WAVEFORM4_REG_DDSX_CONFIG 0x0045 |
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#define | WAVEFORM4_REG_TW_RAM_CONFIG 0x0047 |
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#define | WAVEFORM4_REG_START_DLY4 0x0050 |
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#define | WAVEFORM4_REG_START_ADDR4 0x0051 |
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#define | WAVEFORM4_REG_STOP_ADDR4 0x0052 |
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#define | WAVEFORM4_REG_DDS_CYC4 0x0053 |
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#define | WAVEFORM4_REG_START_DLY3 0x0054 |
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#define | WAVEFORM4_REG_START_ADDR3 0x0055 |
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#define | WAVEFORM4_REG_STOP_ADDR3 0x0056 |
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#define | WAVEFORM4_REG_DDS_CYC3 0x0057 |
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#define | WAVEFORM4_REG_START_DLY2 0x0058 |
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#define | WAVEFORM4_REG_START_ADDR2 0x0059 |
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#define | WAVEFORM4_REG_STOP_ADDR2 0x005A |
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#define | WAVEFORM4_REG_DDS_CYC2 0x005B |
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#define | WAVEFORM4_REG_START_DLY1 0x005C |
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#define | WAVEFORM4_REG_START_ADDR1 0x005D |
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#define | WAVEFORM4_REG_STOP_ADDR1 0x005E |
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#define | WAVEFORM4_REG_DDS_CYC1 0x005F |
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#define | WAVEFORM4_REG_CFG_ERROR 0x0060 |
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#define | WAVEFORM4_SRAM_ADDRESS_MIN 0x6000 |
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#define | WAVEFORM4_SRAM_ADDRESS_MAX 0x6FFF |
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