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#define | M2M_STA_CMD_BASE 4 |
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#define | M2M_CONFIG_CMD_BASE |
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#define | M2M_AP_CMD_BASE 7 |
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#define | M2M_SERVER_CMD_BASE 10 |
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#define | M2M_GEN_CMD_BASE 10 |
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#define | M2M_OTA_CMD_BASE 100 |
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#define | WIFI8_CMD_INTERNAL_WRITE 0xc3 |
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#define | WIFI8_CMD_INTERNAL_READ 0xc4 |
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#define | WIFI8_CMD_DMA_EXT_WRITE 0xc7 |
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#define | WIFI8_CMD_DMA_EXT_READ 0xc8 |
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#define | WIFI8_CMD_SINGLE_WRITE 0xc9 |
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#define | WIFI8_CMD_SINGLE_READ 0xca |
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#define | WIFI8_CMD_RESET 0xcf |
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#define | WIFI8_SPI_RESP_RETRY_COUNT (10) |
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#define | WIFI8_SPI_RETRY_COUNT (10) |
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#define | WIFI8_DATA_PKT_SZ_256 256 |
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#define | WIFI8_DATA_PKT_SZ_512 512 |
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#define | WIFI8_DATA_PKT_SZ_1K 1024 |
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#define | WIFI8_DATA_PKT_SZ_4K (4 * 1024) |
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#define | WIFI8_DATA_PKT_SZ_8K (8 * 1024) |
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#define | WIFI8_DATA_PKT_SZ WIFI8_DATA_PKT_SZ_8K |
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#define | PROGRAM_START 0x26961735ul |
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#define | BOOT_SUCCESS 0x10add09eul |
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#define | BOOT_START 0x12345678ul |
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#define | NBIT31 (0x80000000ul) |
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#define | NBIT30 (0x40000000ul) |
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#define | NBIT29 (0x20000000ul) |
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#define | NBIT28 (0x10000000ul) |
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#define | NBIT27 (0x08000000ul) |
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#define | NBIT26 (0x04000000ul) |
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#define | NBIT25 (0x02000000ul) |
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#define | NBIT24 (0x01000000ul) |
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#define | NBIT23 (0x00800000ul) |
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#define | NBIT22 (0x00400000ul) |
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#define | NBIT21 (0x00200000ul) |
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#define | NBIT20 (0x00100000ul) |
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#define | NBIT19 (0x00080000ul) |
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#define | NBIT18 (0x00040000ul) |
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#define | NBIT17 (0x00020000ul) |
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#define | NBIT16 (0x00010000ul) |
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#define | NBIT15 (0x00008000ul) |
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#define | NBIT14 (0x00004000ul) |
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#define | NBIT13 (0x00002000ul) |
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#define | NBIT12 (0x00001000ul) |
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#define | NBIT11 (0x00000800ul) |
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#define | NBIT10 (0x00000400ul) |
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#define | NBIT9 (0x00000200ul) |
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#define | NBIT8 (0x00000100ul) |
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#define | NBIT7 (0x00000080ul) |
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#define | NBIT6 (0x00000040ul) |
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#define | NBIT5 (0x00000020ul) |
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#define | NBIT4 (0x00000010ul) |
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#define | NBIT3 (0x00000008ul) |
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#define | NBIT2 (0x00000004ul) |
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#define | NBIT1 (0x00000002ul) |
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#define | NBIT0 (0x00000001ul) |
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#define | NMI_PERIPH_REG_BASE 0x1000 |
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#define | NMI_CHIPID (NMI_PERIPH_REG_BASE) |
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#define | rNMI_GP_REG_0 (0x149c) |
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#define | rNMI_GP_REG_1 (0x14A0) |
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#define | rNMI_GLB_RESET (0x1400) |
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#define | rNMI_BOOT_RESET_MUX (0x1118) |
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#define | NMI_STATE_REG (0x108c) |
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#define | BOOTROM_REG (0xc000cul) |
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#define | NMI_REV_REG (0x207acul) /*Also, Used to load ATE firmware from SPI Flash and to ensure that it is running too*/ |
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#define | M2M_WAIT_FOR_HOST_REG (0x207bcul) |
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#define | M2M_FINISH_INIT_STATE 0x02532636ul |
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#define | M2M_FINISH_BOOT_ROM 0x10add09eul |
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#define | M2M_START_FIRMWARE 0xef522f61ul |
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#define | M2M_START_PS_FIRMWARE 0x94992610ul |
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#define | M2M_ATE_FW_START_VALUE (0x3C1CD57Dul) /*Also, Change this value in boot_firmware if it will be changed here*/ |
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#define | M2M_ATE_FW_IS_UP_VALUE (0xD75DC1C3ul) /*Also, Change this value in ATE (Burst) firmware if it will be changed here*/ |
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#define | REV_2B0 (0x2B0) |
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#define | REV_B0 (0x2B0) |
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#define | REV_3A0 (0x3A0) |
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#define | CHIP_ID_3000D (0x3000D0ul) |
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#define | GET_CHIPID() nmi_get_chipid() |
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#define | ISNMC1000(id) (((id & 0xfffff000ul) == 0x100000ul) ? 1 : 0) |
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#define | ISNMC1500(id) (((id & 0xfffff000ul) == 0x150000ul) ? 1 : 0) |
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#define | ISNMC3400(id) (((id & 0xfff0f000ul) == 0x300000ul) ? 1 : 0) |
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#define | REV(id) (((id)&0x00000ffful)) |
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#define | EFUSED_MAC(value) (value & 0xffff0000ul) |
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#define | rHAVE_SDIO_IRQ_GPIO_BIT (NBIT0) |
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#define | rHAVE_USE_PMU_BIT (NBIT1) |
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#define | rHAVE_SLEEP_CLK_SRC_RTC_BIT (NBIT2) |
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#define | rHAVE_SLEEP_CLK_SRC_XO_BIT (NBIT3) |
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#define | rHAVE_EXT_PA_INV_TX_RX (NBIT4) |
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#define | rHAVE_LEGACY_RF_SETTINGS (NBIT5) |
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#define | rHAVE_LOGS_DISABLED_BIT (NBIT6) |
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#define | rHAVE_ETHERNET_MODE_BIT (NBIT7) |
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#define | NMI_GLB_RESET_0 (NMI_PERIPH_REG_BASE + 0x400) |
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#define | NMI_INTR_REG_BASE (NMI_PERIPH_REG_BASE + 0xa00) |
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#define | NMI_PIN_MUX_0 (NMI_PERIPH_REG_BASE + 0x408) |
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#define | NMI_INTR_ENABLE (NMI_INTR_REG_BASE) |
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#define | GET_UINT32(X, Y) (X[0 + Y] + ((uint32_t)X[1 + Y] << 8) + ((uint32_t)X[2 + Y] << 16) + ((uint32_t)X[3 + Y] << 24)) |
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#define | M2M_HIF_INFO_SHIFT (0) |
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#define | M2M_HIF_INFO_MASK (0xffff) |
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#define | M2M_HIF_BLOCK_SHIFT (14) |
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#define | M2M_HIF_BLOCK_MASK (0x3) |
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#define | M2M_HIF_LEVEL_SHIFT (0) |
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#define | M2M_HIF_LEVEL_MASK (0x3fff) |
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#define | M2M_HIF_MAJOR_SHIFT (8) |
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#define | M2M_HIF_MAJOR_MASK (0x3f) |
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#define | M2M_HIF_MINOR_SHIFT (0) |
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#define | M2M_HIF_MINOR_MASK (0xff) |
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#define | M2M_GET_HIF_INFO(hif_ver) ((uint16_t)(((hif_ver) >> M2M_HIF_INFO_SHIFT) & M2M_HIF_INFO_MASK)) |
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#define | M2M_GET_HIF_BLOCK(hif_info) ((uint8_t)(((hif_info) >> M2M_HIF_BLOCK_SHIFT) & M2M_HIF_BLOCK_MASK)) |
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#define | M2M_GET_HIF_LEVEL(hif_info) ((uint16_t)(((hif_info) >> M2M_HIF_LEVEL_SHIFT) & M2M_HIF_LEVEL_MASK)) |
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#define | M2M_GET_HIF_MAJOR(hif_info) ((uint8_t)(((hif_info) >> M2M_HIF_MAJOR_SHIFT) & M2M_HIF_MAJOR_MASK)) |
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#define | M2M_GET_HIF_MINOR(hif_info) ((uint8_t)(((hif_info) >> M2M_HIF_MINOR_SHIFT) & M2M_HIF_MINOR_MASK)) |
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#define | M2M_MAKE_HIF_INFO(hif_level) |
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#define | M2M_AUTH_1X_USER_LEN_MAX 100 |
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#define | M2M_AUTH_1X_PASSWORD_LEN_MAX 256 |
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#define | M2M_HIF_BLOCK_VALUE (2 |
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#define | M2M_HIF_MAJOR_VALUE (1 |
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#define | M2M_HIF_MINOR_VALUE (4 |
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#define | TCP_SOCK_MAX (7 |
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#define | UDP_SOCK_MAX |
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#define | RAW_SOCK_MAX 1 |
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#define | MAX_SOCKET (TCP_SOCK_MAX + UDP_SOCK_MAX + RAW_SOCK_MAX) |
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#define | SOCKET_BUFFER_SIZE 1472 |
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#define | TLS_RECORD_HEADER_LENGTH (5) |
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#define | ETHERNET_HEADER_OFFSET (34) |
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#define | ETHERNET_HEADER_LENGTH (14) |
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#define | TCP_IP_HEADER_LENGTH (40) |
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#define | UDP_IP_HEADER_LENGTH (28) |
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#define | IP_PACKET_OFFSET (ETHERNET_HEADER_LENGTH + ETHERNET_HEADER_OFFSET - M2M_HIF_HDR_OFFSET) |
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#define | TCP_TX_PACKET_OFFSET (IP_PACKET_OFFSET + TCP_IP_HEADER_LENGTH) |
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#define | UDP_TX_PACKET_OFFSET (IP_PACKET_OFFSET + UDP_IP_HEADER_LENGTH) |
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#define | SSL_TX_PACKET_OFFSET (TCP_TX_PACKET_OFFSET + TLS_RECORD_HEADER_LENGTH) |
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#define | SOCKET_REQUEST(ctx, req_id, req_args, req_size, req_payload, req_payload_size, req_payload_offset) hif_send(ctx, M2M_REQ_GROUP_IP, req_id, req_args, req_size, req_payload, req_payload_size, req_payload_offset) |
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#define | SSL_FLAGS_ACTIVE NBIT0 |
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#define | M2M_802_1X_UNENCRYPTED_USERNAME_FLAG 0x80 |
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#define | M2M_802_1X_PREPEND_DOMAIN_FLAG 0x4 |
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#define | M2M_802_1X_MSCHAP2_FLAG 0x0 |
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#define | SOCKET_CMD_BIND 0x41 |
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#define | SOCKET_CMD_LISTEN 0x42 |
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#define | SOCKET_CMD_ACCEPT 0x43 |
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#define | SOCKET_CMD_CONNECT 0x44 |
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#define | SOCKET_CMD_SEND 0x45 |
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#define | SOCKET_CMD_RECV 0x46 |
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#define | SOCKET_CMD_SENDTO 0x47 |
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#define | SOCKET_CMD_RECVFROM 0x48 |
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#define | SOCKET_CMD_CLOSE 0x49 |
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#define | SOCKET_CMD_DNS_RESOLVE 0x4A |
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#define | SOCKET_CMD_SSL_CONNECT 0x4B |
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#define | SOCKET_CMD_SSL_SEND 0x4C |
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#define | SOCKET_CMD_SSL_RECV 0x4D |
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#define | SOCKET_CMD_SSL_CLOSE 0x4E |
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#define | SOCKET_CMD_SET_SOCKET_OPTION 0x4F |
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#define | SOCKET_CMD_SSL_CREATE 0x50 |
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#define | SOCKET_CMD_SSL_SET_SOCK_OPT 0x51 |
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#define | SOCKET_CMD_PING 0x52 |
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#define | SOCKET_CMD_SSL_CONNECT_ALPN 0x53 |
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#define | SOCKET_CMD_RAW_SET_SOCK_OPT 0x54 |
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#define | PING_ERR_SUCCESS 0 |
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#define | PING_ERR_DEST_UNREACH 1 |
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#define | PING_ERR_TIMEOUT 2 |
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#define | HOSTNAME_MAX_SIZE 100 |
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#define | AF_INET 2 |
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#define | SOCK_ERR_NO_ERROR 0 |
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#define | SOCK_STREAM 1 |
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#define | SOCK_DGRAM 2 |
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#define | SOCK_RAW 3 |
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#define | SOCKET_FLAGS_SSL 0x01 |
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#define | SOCKET_FLAGS_IPPROTO_RAW 0x02 |
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#define | RAW_SOCK_ID (TCP_SOCK_MAX + UDP_SOCK_MAX) |
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#define | _htons(A) (uint16_t)((((uint16_t)(A)) << 8) | (((uint16_t)(A)) >> 8)) |
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#define | NM_BSP_B_L_32(x) (x) |
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#define | NM_BSP_B_L_16(x) (x) |
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#define | NMI_PERIPH_REG_BASE 0x1000 |
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#define | NMI_CHIPID (NMI_PERIPH_REG_BASE) |
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#define | NMI_PIN_MUX_0 (NMI_PERIPH_REG_BASE + 0x408) |
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#define | NMI_INTR_ENABLE (NMI_INTR_REG_BASE) |
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#define | NMI_SPI_REG_BASE 0xe800 |
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#define | NMI_SPI_CTL (NMI_SPI_REG_BASE) |
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#define | NMI_SPI_MASTER_DMA_ADDR (NMI_SPI_REG_BASE + 0x4) |
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#define | NMI_SPI_MASTER_DMA_COUNT (NMI_SPI_REG_BASE + 0x8) |
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#define | NMI_SPI_SLAVE_DMA_ADDR (NMI_SPI_REG_BASE + 0xc) |
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#define | NMI_SPI_SLAVE_DMA_COUNT (NMI_SPI_REG_BASE + 0x10) |
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#define | NMI_SPI_TX_MODE (NMI_SPI_REG_BASE + 0x20) |
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#define | NMI_SPI_PROTOCOL_CONFIG (NMI_SPI_REG_BASE + 0x24) |
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#define | NMI_SPI_INTR_CTL (NMI_SPI_REG_BASE + 0x2c) |
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#define | NMI_SPI_PROTOCOL_OFFSET (NMI_SPI_PROTOCOL_CONFIG - NMI_SPI_REG_BASE) |
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#define | NMI_GLB_RESET_0 (NMI_PERIPH_REG_BASE + 0x400) |
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#define | NMI_INTR_REG_BASE (NMI_PERIPH_REG_BASE + 0xa00) |
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#define | NMI_PIN_MUX_0 (NMI_PERIPH_REG_BASE + 0x408) |
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#define | NMI_INTR_ENABLE (NMI_INTR_REG_BASE) |
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#define | CORT_HOST_COMM (0x14) |
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#define | HOST_CORT_COMM (0x0e) |
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#define | WAKE_CLK_REG (0x1) |
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#define | CLOCKS_EN_REG (0x13) |
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#define | TIMEOUT (2000) |
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#define | WAKEUP_TRIALS (4) |
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#define | NMI_AHB_DATA_MEM_BASE 0x30000ul |
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#define | NMI_AHB_SHARE_MEM_BASE 0xd0000ul |
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#define | WIFI_HOST_RCV_CTRL_0 (0x1070) |
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#define | WIFI_HOST_RCV_CTRL_1 (0x1084) |
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#define | WIFI_HOST_RCV_CTRL_2 (0x1078) |
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#define | WIFI_HOST_RCV_CTRL_3 (0x106c) |
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#define | WIFI_HOST_RCV_CTRL_4 (0x150400ul) |
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#define | INTERRUPT_CORTUS_0_3000D0 (0x10a8) |
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#define | INTERRUPT_CORTUS_1_3000D0 (0x10ac) |
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#define | INTERRUPT_CORTUS_2_3000D0 (0x10b0) |
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#define | INTERRUPT_CORTUS_3_3000D0 (0x10b4) |
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#define | M2M_HIF_MAX_PACKET_SIZE (1600 - 4) |
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#define | M2M_HIF_HDR_OFFSET (sizeof(wifi8_hif_hdr_t) + 4) |
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#define | SOCKET_BUFFER_MAX_LENGTH 1400 |
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#define | M2M_MAX_GRP_NUM_REQ (127) |
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#define | SOCKET_CMD_RAW_SET_SOCK_OPT 0x54 |
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#define | HIF_OTA_RB_ONLY 0xFFFF |
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#define | HIFCODE_OTA_RB ((M2M_REQ_GROUP_OTA << 8) | M2M_OTA_REQ_ROLLBACK) |
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#define | HIFCODE_OTA_SW ((M2M_REQ_GROUP_OTA << 8) | M2M_OTA_REQ_SWITCH_FIRMWARE) |
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#define | HIFCODE_SSL_WRITECERT ((M2M_REQ_GROUP_SSL << 8) | M2M_SSL_REQ_WRITE_OWN_CERTS) |
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#define | HIFCODE_WIFI_PASSIVESCAN ((M2M_REQ_GROUP_WIFI << 8) | M2M_WIFI_REQ_PASSIVE_SCAN) |
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#define | HIFCODE_WIFI_CONN ((M2M_REQ_GROUP_WIFI << 8) | M2M_WIFI_REQ_CONN) |
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#define | HIFCODE_WIFI_CONN_PARAM ((M2M_REQ_GROUP_WIFI << 8) | M2M_WIFI_IND_CONN_PARAM) |
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#define | HIFCODE_WIFI_DELETE_CRED ((M2M_REQ_GROUP_WIFI << 8) | M2M_WIFI_REQRSP_DELETE_APID) |
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#define | HIFCODE_WIFI_START_PROV_MODE ((M2M_REQ_GROUP_WIFI << 8) | M2M_WIFI_REQ_START_PROVISION_MODE) |
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#define | HIFCODE_WIFI_ENABLE_AP ((M2M_REQ_GROUP_WIFI << 8) | M2M_WIFI_REQ_ENABLE_AP) |
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#define | HIFCODE_IP_RAW_SOCK_OPT ((M2M_REQ_GROUP_IP << 8) | SOCKET_CMD_RAW_SET_SOCK_OPT) |
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#define | NMI_PERIPH_REG_BASE 0x1000 |
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#define | NMI_CHIPID (NMI_PERIPH_REG_BASE) |
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#define | NMI_PIN_MUX_0 (NMI_PERIPH_REG_BASE + 0x408) |
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#define | NMI_INTR_ENABLE (NMI_INTR_REG_BASE) |
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#define | NMI_SPI_REG_BASE 0xe800 |
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#define | NMI_SPI_CTL (NMI_SPI_REG_BASE) |
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#define | NMI_SPI_MASTER_DMA_ADDR (NMI_SPI_REG_BASE + 0x4) |
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#define | NMI_SPI_MASTER_DMA_COUNT (NMI_SPI_REG_BASE + 0x8) |
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#define | NMI_SPI_SLAVE_DMA_ADDR (NMI_SPI_REG_BASE + 0xc) |
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#define | NMI_SPI_SLAVE_DMA_COUNT (NMI_SPI_REG_BASE + 0x10) |
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#define | NMI_SPI_TX_MODE (NMI_SPI_REG_BASE + 0x20) |
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#define | NMI_SPI_PROTOCOL_CONFIG (NMI_SPI_REG_BASE + 0x24) |
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#define | NMI_SPI_INTR_CTL (NMI_SPI_REG_BASE + 0x2c) |
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#define | NMI_SPI_PROTOCOL_OFFSET (NMI_SPI_PROTOCOL_CONFIG - NMI_SPI_REG_BASE) |
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#define | SPI_BASE NMI_SPI_REG_BASE |
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#define | SPI_RESP_RETRY_COUNT (10) |
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#define | SPI_RETRY_COUNT (10) |
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#define | DATA_PKT_SZ_256 256 |
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#define | DATA_PKT_SZ_512 512 |
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#define | DATA_PKT_SZ_1K 1024 |
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#define | DATA_PKT_SZ_4K (4 * 1024) |
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#define | DATA_PKT_SZ_8K (8 * 1024) |
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#define | DATA_PKT_SZ DATA_PKT_SZ_8K |
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#define | NEW_HIF_LIST |
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#define | WIFI_1X_TLS_HS_FLAGS_PEER_AUTH NBIT1 |
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#define | WIFI_1X_TLS_HS_FLAGS_PEER_CERTTIMECHECK NBIT2 |
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#define | WIFI_1X_TLS_HS_FLAGS_REQUIRE_TIME NBIT3 |
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#define | WIFI_1X_TLS_HS_FLAGS_SESSION_CACHING NBIT4 |
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#define | WIFI_1X_TLS_HS_FLAGS_SPECIFY_ROOTCERT NBIT6 |
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#define | WIFI_1X_TLS_HS_FLAGS_DEFAULT |
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#define | HIF_BLACKLIST_SZ (sizeof(gau16_hif_blacklist) / sizeof(gau16_hif_blacklist[0])) |
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#define | WEP_104_KEY_SIZE ((uint8_t)13) |
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#define | PSK_CALC_LEN 40 |
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#define | M2M_MAC_ADDRES_LEN 6 |
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#define | MAX_TRX_CFG_SZ 8 |
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#define | M2M_CRED_ENCRYPT_FLAG 0x02 |
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#define | M2M_WIFI_CONN_BSSID_FLAG 0x01 |
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#define | M2M_CRED_STORE_FLAG 0x01 |
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#define | M2M_OTA_CMD_BASE 100 |
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#define | M2M_MAX_GRP_NUM_REQ (127) |
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#define | WEP_40_KEY_SIZE ((uint8_t)5) |
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#define | WEP_104_KEY_SIZE ((uint8_t)13) |
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#define | WEP_40_KEY_STRING_SIZE ((uint8_t)10) |
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#define | WEP_104_KEY_STRING_SIZE ((uint8_t)26) |
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#define | WEP_KEY_MAX_INDEX ((uint8_t)4) |
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#define | M2M_SCAN_DEFAULT_NUM_SLOTS (2) |
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#define | M2M_SCAN_DEFAULT_SLOT_TIME (20) |
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#define | M2M_SCAN_DEFAULT_PASSIVE_SLOT_TIME (300) |
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#define | M2M_SCAN_DEFAULT_NUM_PROBE (2) |
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#define | M2M_FASTCONNECT_DEFAULT_RSSI_THRESH (-45) |
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#define | NM_BUS_MAX_TRX_SZ 256 |
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#define | M2M_MAX_SSID_LEN 33 |
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#define | WEP_104_KEY_STRING_SIZE ((uint8_t)26) |
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#define | M2M_MAX_PSK_LEN 65 |
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#define | __PADDING_TSTR_M2MWPS_INFO_ (4 - ((2 + M2M_MAX_SSID_LEN + M2M_MAX_PSK_LEN) % 4)) |
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#define | __padding_tstr_system_time_ (4 - (7 % 4)) |
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