accel20.h

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/****************************************************************************
** Copyright (C) 2020 MikroElektronika d.o.o.
** Contact: https://www.mikroe.com/contact
**
** Permission is hereby granted, free of charge, to any person obtaining a copy
** of this software and associated documentation files (the "Software"), to deal
** in the Software without restriction, including without limitation the rights
** to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
** copies of the Software, and to permit persons to whom the Software is
** furnished to do so, subject to the following conditions:
** The above copyright notice and this permission notice shall be
** included in all copies or substantial portions of the Software.
**
** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
**  USE OR OTHER DEALINGS IN THE SOFTWARE.
****************************************************************************/
 
#ifndef ACCEL20_H
#define ACCEL20_H
 
#ifdef __cplusplus
extern "C"{
#endif
 
#ifdef PREINIT_SUPPORTED
#include "preinit.h"
#endif
 
#ifdef MikroCCoreVersion
    #if MikroCCoreVersion >= 1
        #include "delays.h"
    #endif
#endif
 
#include "drv_digital_out.h"
#include "drv_digital_in.h"
#include "drv_i2c_master.h"
#include "drv_spi_master.h"
#include "spi_specifics.h"
 
#define ACCEL20_REG_MAN_ID           0x00
#define ACCEL20_REG_PART_ID          0x01
#define ACCEL20_REG_XADP_L           0x02
#define ACCEL20_REG_XADP_H           0x03
#define ACCEL20_REG_YADP_L           0x04
#define ACCEL20_REG_YADP_H           0x05
#define ACCEL20_REG_ZADP_L           0x06
#define ACCEL20_REG_ZADP_H           0x07
#define ACCEL20_REG_XOUT_L           0x08
#define ACCEL20_REG_XOUT_H           0x09
#define ACCEL20_REG_YOUT_L           0x0A
#define ACCEL20_REG_YOUT_H           0x0B
#define ACCEL20_REG_ZOUT_L           0x0C
#define ACCEL20_REG_ZOUT_H           0x0D
#define ACCEL20_REG_COTR             0x12
#define ACCEL20_REG_WHO_AM_I         0x13
#define ACCEL20_REG_TSCP             0x14
#define ACCEL20_REG_TSPP             0x15
#define ACCEL20_REG_INS1             0x16
#define ACCEL20_REG_INS2             0x17
#define ACCEL20_REG_INS3             0x18
#define ACCEL20_REG_STATUS_REG       0x19
#define ACCEL20_REG_INT_REL          0x1A
#define ACCEL20_REG_CNTL1            0x1B
#define ACCEL20_REG_CNTL2            0x1C
#define ACCEL20_REG_CNTL3            0x1D
#define ACCEL20_REG_CNTL4            0x1E
#define ACCEL20_REG_CNTL5            0x1F
#define ACCEL20_REG_CNTL6            0x20
#define ACCEL20_REG_ODCNTL           0x21
#define ACCEL20_REG_INC1             0x22
#define ACCEL20_REG_INC2             0x23
#define ACCEL20_REG_INC3             0x24
#define ACCEL20_REG_INC4             0x25
#define ACCEL20_REG_INC5             0x26
#define ACCEL20_REG_INC6             0x27
#define ACCEL20_REG_TILT_TIMER       0x29
#define ACCEL20_REG_TDTRC            0x2A
#define ACCEL20_REG_TDTC             0x2B
#define ACCEL20_REG_TTH              0x2C
#define ACCEL20_REG_TTL              0x2D
#define ACCEL20_REG_FTD              0x2E
#define ACCEL20_REG_STD              0x2F
#define ACCEL20_REG_TLT              0x30
#define ACCEL20_REG_TWS              0x31
#define ACCEL20_REG_FFTH             0x32
#define ACCEL20_REG_FFC              0x33
#define ACCEL20_REG_FFCNTL           0x34
#define ACCEL20_REG_TILT_ANGLE_LL    0x37
#define ACCEL20_REG_TILT_ANGLE_HL    0x38
#define ACCEL20_REG_HYST_SET         0x39
#define ACCEL20_REG_LP_CNTL1         0x3A
#define ACCEL20_REG_LP_CNTL2         0x3B
#define ACCEL20_REG_WUFTH            0x49
#define ACCEL20_REG_BTSWUFTH         0x4A
#define ACCEL20_REG_BTSTH            0x4B
#define ACCEL20_REG_BTSC             0x4C
#define ACCEL20_REG_WUFC             0x4D
#define ACCEL20_REG_SELF_TEST        0x5D
#define ACCEL20_REG_BUF_CNTL1        0x5E
#define ACCEL20_REG_BUF_CNTL2        0x5F
#define ACCEL20_REG_BUF_STATUS_1     0x60
#define ACCEL20_REG_BUF_STATUS_2     0x61
#define ACCEL20_REG_BUF_CLEAR        0x62
#define ACCEL20_REG_BUF_READ         0x63
#define ACCEL20_REG_ADP_CNTL1        0x64
#define ACCEL20_REG_ADP_CNTL2        0x65
#define ACCEL20_REG_ADP_CNTL3        0x66
#define ACCEL20_REG_ADP_CNTL4        0x67
#define ACCEL20_REG_ADP_CNTL5        0x68
#define ACCEL20_REG_ADP_CNTL6        0x69
#define ACCEL20_REG_ADP_CNTL7        0x6A
#define ACCEL20_REG_ADP_CNTL8        0x6B
#define ACCEL20_REG_ADP_CNTL9        0x6C
#define ACCEL20_REG_ADP_CNTL10       0x6D
#define ACCEL20_REG_ADP_CNTL11       0x6E
#define ACCEL20_REG_ADP_CNTL12       0x6F
#define ACCEL20_REG_ADP_CNTL13       0x70
#define ACCEL20_REG_ADP_CNTL14       0x71
#define ACCEL20_REG_ADP_CNTL15       0x72
#define ACCEL20_REG_ADP_CNTL16       0x73
#define ACCEL20_REG_ADP_CNTL17       0x74
#define ACCEL20_REG_ADP_CNTL18       0x75
#define ACCEL20_REG_ADP_CNTL19       0x76
#define ACCEL20_REG_INTERNAL         0x7F
 
 // accel20_reg
 
#define ACCEL20_INTERNAL_SOFT_RESET  0x00
#define ACCEL20_SOFT_RESET_PWR_CYC   0x00
#define ACCEL20_SOFT_RESET_REBOOT    0x80
 
#define ACCEL20_CNTL1_RANGE_8g       0x00
#define ACCEL20_CNTL1_RANGE_16g      0x01
#define ACCEL20_CNTL1_RANGE_32g      0x02
#define ACCEL20_CNTL1_RANGE_64g      0x03
#define ACCEL20_RANGE_BIT_MASK       0xE7
 
#define ACCEL20_ODCNTL_ODR_0_781_Hz  0x00
#define ACCEL20_ODCNTL_ODR_1_563_Hz  0x01
#define ACCEL20_ODCNTL_ODR_3_125_Hz  0x02
#define ACCEL20_ODCNTL_ODR_6_25_Hz   0x03
#define ACCEL20_ODCNTL_ODR_12_5_Hz   0x04
#define ACCEL20_ODCNTL_ODR_25_Hz     0x05
#define ACCEL20_ODCNTL_ODR_50_Hz     0x06
#define ACCEL20_ODCNTL_ODR_100_Hz    0x07
#define ACCEL20_ODCNTL_ODR_200_Hz    0x08
#define ACCEL20_ODCNTL_ODR_400_Hz    0x09
#define ACCEL20_ODCNTL_ODR_800_Hz    0x0A
#define ACCEL20_ODCNTL_ODR_1600_Hz   0x0B
#define ACCEL20_ODCNTL_ODR_3200_Hz   0x0C
#define ACCEL20_ODCNTL_ODR_6400_Hz   0x0D
#define ACCEL20_ODCNTL_ODR_12800_Hz  0x0E
#define ACCEL20_ODCNTL_ODR_25600_Hz  0x0F
#define ACCEL20_ODR_BIT_MASK         0x0F
 
#define ACCEL20_CNTL1_OP_MODE_STB    0x00
#define ACCEL20_CNTL1_OP_MODE_L_PWR  0x02
#define ACCEL20_CNTL1_OP_MODE_HP     0x03
#define ACCEL20_OP_MODE_BIT_MASK     0xC0
 
#define ACCEL20_ENABLE_INT_1         0x30
#define ACCEL20_ENABLE_DATA_READY    0x10
 
#define ACCEL20_DATA_READY_BIT_MASK  0x10
 
#define ACCEL20_INT1_DATA_READY      0x00
 
#define ACCEL20_CHIP_ID              0x46
 
#define ACCEL20_TRIGGER_DISABLE      0x00
#define ACCEL20_TRIGGER_ENABLE       0x01
 
#define ACCEL20_SET_DEV_ADDR_GND     0x1E
#define ACCEL20_SET_DEV_ADDR_VCC     0x1F
 
#define ACCEL20_SET_DATA_SAMPLE_EDGE      SET_SPI_DATA_SAMPLE_EDGE
#define ACCEL20_SET_DATA_SAMPLE_MIDDLE    SET_SPI_DATA_SAMPLE_MIDDLE
 
 // accel20_set
 
#define ACCEL20_MAP_MIKROBUS( cfg, mikrobus )       \
    cfg.scl  = MIKROBUS( mikrobus, MIKROBUS_SCL );  \
    cfg.sda  = MIKROBUS( mikrobus, MIKROBUS_SDA );  \
    cfg.miso = MIKROBUS( mikrobus, MIKROBUS_MISO ); \
    cfg.mosi = MIKROBUS( mikrobus, MIKROBUS_MOSI ); \
    cfg.sck  = MIKROBUS( mikrobus, MIKROBUS_SCK );  \
    cfg.cs   = MIKROBUS( mikrobus, MIKROBUS_CS );   \
    cfg.i2 = MIKROBUS( mikrobus, MIKROBUS_AN );     \
    cfg.trg = MIKROBUS( mikrobus, MIKROBUS_PWM );   \
    cfg.i1 = MIKROBUS( mikrobus, MIKROBUS_INT )
 
 // accel20_map
 // accel20
 
typedef enum
{
   ACCEL20_DRV_SEL_SPI,      
   ACCEL20_DRV_SEL_I2C       
} accel20_drv_t;
 
typedef err_t ( *accel20_master_io_t )( struct accel20_s*, uint8_t, uint8_t*, uint8_t ); 
typedef struct accel20_s
{
    digital_out_t  trg;     
    digital_in_t  i2;       
    digital_in_t  i1;       
    i2c_master_t  i2c;      
    spi_master_t  spi;      
    uint8_t     slave_address;     
    pin_name_t  chip_select;       
   accel20_drv_t  drv_sel;         
   accel20_master_io_t  write_f;   
   accel20_master_io_t  read_f;    
} accel20_t;
 
typedef struct
{
    pin_name_t  scl;        
    pin_name_t  sda;        
    pin_name_t  miso;       
    pin_name_t  mosi;       
    pin_name_t  sck;        
    pin_name_t  cs;         
    pin_name_t  i2;         
    pin_name_t  trg;        
    pin_name_t  i1;         
    uint32_t  i2c_speed;                                
    uint8_t   i2c_address;                              
    uint32_t                           spi_speed;       
    spi_master_mode_t                  spi_mode;        
    spi_master_chip_select_polarity_t  cs_polarity;     
   accel20_drv_t  drv_sel;                              
} accel20_cfg_t;
 
typedef struct
{
    int16_t x;
    int16_t y;
    int16_t z;
 
} accel20_axis_t;
 
typedef enum
{
   ACCEL20_OK = 0,
   ACCEL20_ERROR = -1
 
} accel20_return_value_t;
 
void accel20_cfg_setup ( accel20_cfg_t *cfg );
 
void accel20_drv_interface_selection ( accel20_cfg_t *cfg, accel20_drv_t drv_sel );
 
err_t accel20_init ( accel20_t *ctx, accel20_cfg_t *cfg );
 
err_t accel20_default_cfg ( accel20_t *ctx );
 
err_t accel20_generic_write ( accel20_t *ctx, uint8_t reg, uint8_t *data_in, uint8_t len );
 
err_t accel20_generic_read ( accel20_t *ctx, uint8_t reg, uint8_t *data_out, uint8_t len );
 
err_t accel20_soft_reset ( accel20_t *ctx );
 
err_t accel20_check_id ( accel20_t *ctx );
 
uint8_t accel20_data_ready (accel20_t *ctx );
 
err_t accel20_set_operating_mode ( accel20_t *ctx, uint8_t op_mode );
 
err_t accel20_enable_int_1_pin ( accel20_t *ctx );
 
err_t accel20_enable_int_2_pin ( accel20_t *ctx );
 
err_t accel20_set_accel_range ( accel20_t *ctx, uint8_t range );
 
err_t accel20_set_output_data_rate ( accel20_t *ctx, uint8_t odr );
 
err_t accel20_get_axis_data ( accel20_t *ctx, accel20_axis_t *axis );
 
err_t accel20_set_trigger ( accel20_t *ctx, uint8_t en_trg );
 
uint8_t accel20_get_int_1 ( accel20_t *ctx );
 
uint8_t accel20_get_int_2 ( accel20_t *ctx );
 
#ifdef __cplusplus
}
#endif
#endif // ACCEL20_H
 
 // accel20
 
// ------------------------------------------------------------------------ END