Settings for registers of Accel 21 Click driver. More...

Macros
#define	ACCEL21_STATUS_AUX_TDA_BIT_MASK 0x04
	Accel 21 description setting.

#define	ACCEL21_STATUS_AUX_TOR_BIT_MASK 0x40

#define	ACCEL21_TEMP_CFG_TEMP_EN_BIT_MASK 0xC0

#define	ACCEL21_WHO_AM_I 0x33

#define	ACCEL21_OP_MODE_NORMAL 0x00

#define	ACCEL21_OP_MODE_HIGH_RESOLUTION 0x01

#define	ACCEL21_OP_MODE_LOW_POWER 0x02

#define	ACCEL21_OP_MODE_NOT_ALLOWED 0x02

#define	ACCEL21_CTRL_OP_MODE_BIT_MASK 0x08

#define	ACCEL21_STATUS_NEW_DATA_AVL_BIT_MASK 0x08

#define	ACCEL21_STATUS_DATA_OVERRUN_BIT_MASK 0x80

#define	ACCEL21_CTRL_REG1_ODR_PWR_DOWN_MODE 0x00

#define	ACCEL21_CTRL_REG1_ODR_1_Hz 0x01

#define	ACCEL21_CTRL_REG1_ODR_10_Hz 0x02

#define	ACCEL21_CTRL_REG1_ODR_25_Hz 0x03

#define	ACCEL21_CTRL_REG1_ODR_50_Hz 0x04

#define	ACCEL21_CTRL_REG1_ODR_100_Hz 0x05

#define	ACCEL21_CTRL_REG1_ODR_200_Hz 0x06

#define	ACCEL21_CTRL_REG1_ODR_400_Hz 0x07

#define	ACCEL21_CTRL_REG1_ODR_1_62_kHz 0x08

#define	ACCEL21_CTRL_REG1_ODR_1_344_kHz 0x09

#define	ACCEL21_CTRL_REG1_ODR_BIT_MASK 0xF0

#define	ACCEL21_CTRL_REG1_LPEN_DISABLE 0x00

#define	ACCEL21_CTRL_REG1_LPEN_ENABLE 0x01

#define	ACCEL21_CTRL_REG1_LPEN_BIT_MASK 0x08

#define	ACCEL21_CTRL_REG1_XYZEN_DISABLE 0x00

#define	ACCEL21_CTRL_REG1_XYZEN_ENABLE 0x01

#define	ACCEL21_CTRL_REG1_ZEN_BIT_MASK 0x04

#define	ACCEL21_CTRL_REG1_YEN_BIT_MASK 0x02

#define	ACCEL21_CTRL_REG1_XEN_BIT_MASK 0x01

#define	ACCEL21_CTRL_REG4_BDU_CONTIN_UPDATE 0x00

#define	ACCEL21_CTRL_REG4_BDU_NOT_UPDATE 0x01

#define	ACCEL21_CTRL_REG4_BDU_BIT_MASK 0x80

#define	ACCEL21_CTRL_REG4_FS_2_g 0x00

#define	ACCEL21_CTRL_REG4_FS_4_g 0x01

#define	ACCEL21_CTRL_REG4_FS_10_g 0x02

#define	ACCEL21_CTRL_REG4_FS_16_g 0x03

#define	ACCEL21_CTRL_REG4_FS_BIT_MASK 0x30

#define	ACCEL21_CTRL_REG4_HR_DISABLE 0x00

#define	ACCEL21_CTRL_REG4_HR_ENABLE 0x01

#define	ACCEL21_CTRL_REG1_HR_BIT_MASK 0x08

#define	ACCEL21_DEVICE_ADDRESS_GND 0x18
	Accel 21 device address setting.

#define	ACCEL21_DEVICE_ADDRESS_VCC 0x19

#define	ACCEL21_SET_DATA_SAMPLE_EDGE SET_SPI_DATA_SAMPLE_EDGE
	Data sample selection.

#define	ACCEL21_SET_DATA_SAMPLE_MIDDLE SET_SPI_DATA_SAMPLE_MIDDLE

Detailed Description

Settings for registers of Accel 21 Click driver.

Macro Definition Documentation

◆ ACCEL21_CTRL_OP_MODE_BIT_MASK

#define ACCEL21_CTRL_OP_MODE_BIT_MASK 0x08

◆ ACCEL21_CTRL_REG1_HR_BIT_MASK

#define ACCEL21_CTRL_REG1_HR_BIT_MASK 0x08

◆ ACCEL21_CTRL_REG1_LPEN_BIT_MASK

#define ACCEL21_CTRL_REG1_LPEN_BIT_MASK 0x08

◆ ACCEL21_CTRL_REG1_LPEN_DISABLE

#define ACCEL21_CTRL_REG1_LPEN_DISABLE 0x00

◆ ACCEL21_CTRL_REG1_LPEN_ENABLE

#define ACCEL21_CTRL_REG1_LPEN_ENABLE 0x01

◆ ACCEL21_CTRL_REG1_ODR_100_Hz

#define ACCEL21_CTRL_REG1_ODR_100_Hz 0x05

◆ ACCEL21_CTRL_REG1_ODR_10_Hz

#define ACCEL21_CTRL_REG1_ODR_10_Hz 0x02

◆ ACCEL21_CTRL_REG1_ODR_1_344_kHz

#define ACCEL21_CTRL_REG1_ODR_1_344_kHz 0x09

◆ ACCEL21_CTRL_REG1_ODR_1_62_kHz

#define ACCEL21_CTRL_REG1_ODR_1_62_kHz 0x08

◆ ACCEL21_CTRL_REG1_ODR_1_Hz

#define ACCEL21_CTRL_REG1_ODR_1_Hz 0x01

◆ ACCEL21_CTRL_REG1_ODR_200_Hz

#define ACCEL21_CTRL_REG1_ODR_200_Hz 0x06

◆ ACCEL21_CTRL_REG1_ODR_25_Hz

#define ACCEL21_CTRL_REG1_ODR_25_Hz 0x03

◆ ACCEL21_CTRL_REG1_ODR_400_Hz

#define ACCEL21_CTRL_REG1_ODR_400_Hz 0x07

◆ ACCEL21_CTRL_REG1_ODR_50_Hz

#define ACCEL21_CTRL_REG1_ODR_50_Hz 0x04

◆ ACCEL21_CTRL_REG1_ODR_BIT_MASK

#define ACCEL21_CTRL_REG1_ODR_BIT_MASK 0xF0

◆ ACCEL21_CTRL_REG1_ODR_PWR_DOWN_MODE

#define ACCEL21_CTRL_REG1_ODR_PWR_DOWN_MODE 0x00

◆ ACCEL21_CTRL_REG1_XEN_BIT_MASK

#define ACCEL21_CTRL_REG1_XEN_BIT_MASK 0x01

◆ ACCEL21_CTRL_REG1_XYZEN_DISABLE

#define ACCEL21_CTRL_REG1_XYZEN_DISABLE 0x00

◆ ACCEL21_CTRL_REG1_XYZEN_ENABLE

#define ACCEL21_CTRL_REG1_XYZEN_ENABLE 0x01

◆ ACCEL21_CTRL_REG1_YEN_BIT_MASK

#define ACCEL21_CTRL_REG1_YEN_BIT_MASK 0x02

◆ ACCEL21_CTRL_REG1_ZEN_BIT_MASK

#define ACCEL21_CTRL_REG1_ZEN_BIT_MASK 0x04

◆ ACCEL21_CTRL_REG4_BDU_BIT_MASK

#define ACCEL21_CTRL_REG4_BDU_BIT_MASK 0x80

◆ ACCEL21_CTRL_REG4_BDU_CONTIN_UPDATE

#define ACCEL21_CTRL_REG4_BDU_CONTIN_UPDATE 0x00

◆ ACCEL21_CTRL_REG4_BDU_NOT_UPDATE

#define ACCEL21_CTRL_REG4_BDU_NOT_UPDATE 0x01

◆ ACCEL21_CTRL_REG4_FS_10_g

#define ACCEL21_CTRL_REG4_FS_10_g 0x02

◆ ACCEL21_CTRL_REG4_FS_16_g

#define ACCEL21_CTRL_REG4_FS_16_g 0x03

◆ ACCEL21_CTRL_REG4_FS_2_g

#define ACCEL21_CTRL_REG4_FS_2_g 0x00

◆ ACCEL21_CTRL_REG4_FS_4_g

#define ACCEL21_CTRL_REG4_FS_4_g 0x01

◆ ACCEL21_CTRL_REG4_FS_BIT_MASK

#define ACCEL21_CTRL_REG4_FS_BIT_MASK 0x30

◆ ACCEL21_CTRL_REG4_HR_DISABLE

#define ACCEL21_CTRL_REG4_HR_DISABLE 0x00

◆ ACCEL21_CTRL_REG4_HR_ENABLE

#define ACCEL21_CTRL_REG4_HR_ENABLE 0x01

◆ ACCEL21_DEVICE_ADDRESS_GND

#define ACCEL21_DEVICE_ADDRESS_GND 0x18

Accel 21 device address setting.

Specified setting for device slave address selection of Accel 21 Click driver.

◆ ACCEL21_DEVICE_ADDRESS_VCC

#define ACCEL21_DEVICE_ADDRESS_VCC 0x19

◆ ACCEL21_OP_MODE_HIGH_RESOLUTION

#define ACCEL21_OP_MODE_HIGH_RESOLUTION 0x01

◆ ACCEL21_OP_MODE_LOW_POWER

#define ACCEL21_OP_MODE_LOW_POWER 0x02

◆ ACCEL21_OP_MODE_NORMAL

#define ACCEL21_OP_MODE_NORMAL 0x00

◆ ACCEL21_OP_MODE_NOT_ALLOWED

#define ACCEL21_OP_MODE_NOT_ALLOWED 0x02

◆ ACCEL21_SET_DATA_SAMPLE_EDGE

#define ACCEL21_SET_DATA_SAMPLE_EDGE SET_SPI_DATA_SAMPLE_EDGE

Data sample selection.

This macro sets data samples for SPI modules.

Note: Available only on Microchip PIC family devices. This macro will set data sampling for all SPI modules on MCU. Can be overwritten with accel21_init which will set SET_SPI_DATA_SAMPLE_MIDDLE by default on the mapped mikrobus.

◆ ACCEL21_SET_DATA_SAMPLE_MIDDLE

#define ACCEL21_SET_DATA_SAMPLE_MIDDLE SET_SPI_DATA_SAMPLE_MIDDLE

◆ ACCEL21_STATUS_AUX_TDA_BIT_MASK

#define ACCEL21_STATUS_AUX_TDA_BIT_MASK 0x04

Accel 21 description setting.

Specified setting for description of Accel 21 Click driver.

◆ ACCEL21_STATUS_AUX_TOR_BIT_MASK

#define ACCEL21_STATUS_AUX_TOR_BIT_MASK 0x40

◆ ACCEL21_STATUS_DATA_OVERRUN_BIT_MASK

#define ACCEL21_STATUS_DATA_OVERRUN_BIT_MASK 0x80

◆ ACCEL21_STATUS_NEW_DATA_AVL_BIT_MASK

#define ACCEL21_STATUS_NEW_DATA_AVL_BIT_MASK 0x08

◆ ACCEL21_TEMP_CFG_TEMP_EN_BIT_MASK

#define ACCEL21_TEMP_CFG_TEMP_EN_BIT_MASK 0xC0

◆ ACCEL21_WHO_AM_I

#define ACCEL21_WHO_AM_I 0x33

Macros