accel27.h

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/****************************************************************************
** Copyright (C) 2020 MikroElektronika d.o.o.
** Contact: https://www.mikroe.com/contact
**
** Permission is hereby granted, free of charge, to any person obtaining a copy
** of this software and associated documentation files (the "Software"), to deal
** in the Software without restriction, including without limitation the rights
** to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
** copies of the Software, and to permit persons to whom the Software is
** furnished to do so, subject to the following conditions:
** The above copyright notice and this permission notice shall be
** included in all copies or substantial portions of the Software.
**
** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
**  USE OR OTHER DEALINGS IN THE SOFTWARE.
****************************************************************************/
 
#ifndef ACCEL27_H
#define ACCEL27_H
 
#ifdef __cplusplus
extern "C"{
#endif
 
#ifdef PREINIT_SUPPORTED
#include "preinit.h"
#endif
 
#ifdef MikroCCoreVersion
    #if MikroCCoreVersion >= 1
        #include "delays.h"
    #endif
#endif
 
#include "drv_digital_out.h"
#include "drv_digital_in.h"
#include "drv_i2c_master.h"
#include "drv_spi_master.h"
#include "spi_specifics.h"
 
#define ACCEL27_REG_DEVID_AD                0x00
#define ACCEL27_REG_DEVID_MST               0x01
#define ACCEL27_REG_PARTID                  0x02
#define ACCEL27_REG_REVID                   0x03
#define ACCEL27_REG_STATUS                  0x04
#define ACCEL27_REG_STATUS2                 0x05
#define ACCEL27_REG_FIFO_ENTRIES2           0x06
#define ACCEL27_REG_FIFO_ENTRIES            0x07
#define ACCEL27_REG_XDATA_H                 0x08
#define ACCEL27_REG_XDATA_L                 0x09
#define ACCEL27_REG_YDATA_H                 0x0A
#define ACCEL27_REG_YDATA_L                 0x0B
#define ACCEL27_REG_ZDATA_H                 0x0C
#define ACCEL27_REG_ZDATA_L                 0x0D
#define ACCEL27_REG_MAXPEAK_X_H             0x15
#define ACCEL27_REG_MAXPEAK_X_L             0x16
#define ACCEL27_REG_MAXPEAK_Y_H             0x17
#define ACCEL27_REG_MAXPEAK_Y_L             0x18
#define ACCEL27_REG_MAXPEAK_Z_H             0x19
#define ACCEL27_REG_MAXPEAK_Z_L             0x1A
#define ACCEL27_REG_OFFSET_X                0x20
#define ACCEL27_REG_OFFSET_Y                0x21
#define ACCEL27_REG_OFFSET_Z                0x22
#define ACCEL27_REG_THRESH_ACT_X_H          0x23
#define ACCEL27_REG_THRESH_ACT_X_L          0x24
#define ACCEL27_REG_THRESH_ACT_Y_H          0x25
#define ACCEL27_REG_THRESH_ACT_Y_L          0x26
#define ACCEL27_REG_THRESH_ACT_Z_H          0x27
#define ACCEL27_REG_THRESH_ACT_Z_L          0x28
#define ACCEL27_REG_TIME_ACT                0x29
#define ACCEL27_REG_THRESH_INACT_X_H        0x2A
#define ACCEL27_REG_THRESH_INACT_X_L        0x2B
#define ACCEL27_REG_THRESH_INACT_Y_H        0x2C
#define ACCEL27_REG_THRESH_INACT_Y_L        0x2D
#define ACCEL27_REG_THRESH_INACT_Z_H        0x2E
#define ACCEL27_REG_THRESH_INACT_Z_L        0x2F
#define ACCEL27_REG_TIME_INACT_H            0x30
#define ACCEL27_REG_TIME_INACT_L            0x31
#define ACCEL27_REG_THRESH_ACT2_X_H         0x32
#define ACCEL27_REG_THRESH_ACT2_X_L         0x33
#define ACCEL27_REG_THRESH_ACT2_Y_H         0x34
#define ACCEL27_REG_THRESH_ACT2_Y_L         0x35
#define ACCEL27_REG_THRESH_ACT2_Z_H         0x36
#define ACCEL27_REG_THRESH_ACT2_Z_L         0x37
#define ACCEL27_REG_HPF                     0x38
#define ACCEL27_REG_FIFO_SAMPLES            0x39
#define ACCEL27_REG_FIFO_CTL                0x3A
#define ACCEL27_REG_INT1_MAP                0x3B
#define ACCEL27_REG_INT2_MAP                0x3C
#define ACCEL27_REG_TIMING                  0x3D
#define ACCEL27_REG_MEASURE                 0x3E
#define ACCEL27_REG_POWER_CTL               0x3F
#define ACCEL27_REG_SELF_TEST               0x40
#define ACCEL27_REG_RESET                   0x41
#define ACCEL27_REG_FIFO_DATA               0x42
 
 // accel27_reg
 
#define ACCEL27_INT_MAP_INT_LOW             0x80
#define ACCEL27_INT_MAP_AWAKE               0x40
#define ACCEL27_INT_MAP_ACT                 0x20
#define ACCEL27_INT_MAP_INACT               0x10
#define ACCEL27_INT_MAP_DATA_RDY            0x01
 
#define ACCEL27_TIMING_ODR_320HZ            0x00
#define ACCEL27_TIMING_ODR_640HZ            0x20
#define ACCEL27_TIMING_ODR_1280HZ           0x40
#define ACCEL27_TIMING_ODR_25600HZ          0x60
#define ACCEL27_TIMING_ODR_5120HZ           0x80
#define ACCEL27_TIMING_ODR_MASK             0xE0
#define ACCEL27_TIMING_WAKEUP_RATE_65_MS    0x00
#define ACCEL27_TIMING_WAKEUP_RATE_130_MS   0x04
#define ACCEL27_TIMING_WAKEUP_RATE_260_MS   0x08
#define ACCEL27_TIMING_WAKEUP_RATE_640_MS   0x0C
#define ACCEL27_TIMING_WAKEUP_RATE_2560_MS  0x10
#define ACCEL27_TIMING_WAKEUP_RATE_5120_MS  0x14
#define ACCEL27_TIMING_WAKEUP_RATE_10240_MS 0x18
#define ACCEL27_TIMING_WAKEUP_RATE_30720_MS 0x1C
#define ACCEL27_TIMING_WAKEUP_RATE_MASK     0x1C
#define ACCEL27_TIMING_EXT_CLK              0x02
#define ACCEL27_TIMING_EXT_SYNC             0x01
 
#define ACCEL27_POWER_CTL_I2C_HSM_EN        0x80
#define ACCEL27_POWER_CTL_INSTANT_ON_THRESH 0x20
#define ACCEL27_POWER_CTL_FLT_SETL_462_5_MS 0x00
#define ACCEL27_POWER_CTL_FLT_SETL_4_OF_ODR 0x10
#define ACCEL27_POWER_CTL_FLT_SETL_MASK     0x10
#define ACCEL27_POWER_CTL_LPF_DISABLE       0x08
#define ACCEL27_POWER_CTL_HPF_DISABLE       0x04
#define ACCEL27_POWER_CTL_MODE_STANDBY      0x00
#define ACCEL27_POWER_CTL_MODE_WAKE_UP      0x01
#define ACCEL27_POWER_CTL_MODE_INSTANT_ON   0x02
#define ACCEL27_POWER_CTL_MODE_MEASUREMENT  0x03
#define ACCEL27_POWER_CTL_MODE_MASK         0x03
 
#define ACCEL27_RESET                       0x52
 
#define ACCEL27_DEVID_AD                    0xAD
#define ACCEL27_DEVID_MST                   0x1D
#define ACCEL27_DEVID_PRODUCT               0xFA
 
#define ACCEL27_SCALE_FACTOR_LSB_PER_G      5.0f
 
#define ACCEL27_DEVICE_ADDRESS_0            0x1D
#define ACCEL27_DEVICE_ADDRESS_1            0x53
 
#define ACCEL27_SET_DATA_SAMPLE_EDGE        SET_SPI_DATA_SAMPLE_EDGE
#define ACCEL27_SET_DATA_SAMPLE_MIDDLE      SET_SPI_DATA_SAMPLE_MIDDLE
 
 // accel27_set
 
#define ACCEL27_MAP_MIKROBUS( cfg, mikrobus ) \
    cfg.scl  = MIKROBUS( mikrobus, MIKROBUS_SCL ); \
    cfg.sda  = MIKROBUS( mikrobus, MIKROBUS_SDA ); \
    cfg.miso = MIKROBUS( mikrobus, MIKROBUS_MISO ); \
    cfg.mosi = MIKROBUS( mikrobus, MIKROBUS_MOSI ); \
    cfg.sck  = MIKROBUS( mikrobus, MIKROBUS_SCK ); \
    cfg.cs   = MIKROBUS( mikrobus, MIKROBUS_CS ); \
    cfg.int2 = MIKROBUS( mikrobus, MIKROBUS_AN ); \
    cfg.int1 = MIKROBUS( mikrobus, MIKROBUS_INT )
 
 // accel27_map
 // accel27
 
typedef enum
{
    ACCEL27_DRV_SEL_SPI,            
    ACCEL27_DRV_SEL_I2C             
} accel27_drv_t;
 
typedef err_t ( *accel27_master_io_t )( struct accel27_s*, uint8_t, uint8_t*, uint8_t ); 
typedef struct accel27_s
{
    digital_in_t int2;              
    digital_in_t int1;              
    i2c_master_t i2c;               
    spi_master_t spi;               
    uint8_t      slave_address;     
    pin_name_t   chip_select;       
    accel27_drv_t drv_sel;          
    accel27_master_io_t write_f;    
    accel27_master_io_t read_f;     
} accel27_t;
 
typedef struct
{
    pin_name_t scl;                 
    pin_name_t sda;                 
    pin_name_t miso;                
    pin_name_t mosi;                
    pin_name_t sck;                 
    pin_name_t cs;                  
    pin_name_t int2;                
    pin_name_t int1;                
    uint32_t   i2c_speed;           
    uint8_t    i2c_address;         
    uint32_t                          spi_speed;    
    spi_master_mode_t                 spi_mode;     
    spi_master_chip_select_polarity_t cs_polarity;  
    accel27_drv_t drv_sel;          
} accel27_cfg_t;
 
typedef struct
{
    float x;                        
    float y;                        
    float z;                        
} accel27_axes_t;
 
typedef enum
{
    ACCEL27_OK = 0,
    ACCEL27_ERROR = -1
 
} accel27_return_value_t;
 
void accel27_cfg_setup ( accel27_cfg_t *cfg );
 
void accel27_drv_interface_selection ( accel27_cfg_t *cfg, accel27_drv_t drv_sel );
 
err_t accel27_init ( accel27_t *ctx, accel27_cfg_t *cfg );
 
err_t accel27_default_cfg ( accel27_t *ctx );
 
err_t accel27_generic_write ( accel27_t *ctx, uint8_t reg, uint8_t *data_in, uint8_t len );
 
err_t accel27_generic_read ( accel27_t *ctx, uint8_t reg, uint8_t *data_out, uint8_t len );
 
err_t accel27_write_register ( accel27_t *ctx, uint8_t reg, uint8_t data_in );
 
err_t accel27_read_register ( accel27_t *ctx, uint8_t reg, uint8_t *data_out );
 
err_t accel27_check_communication ( accel27_t *ctx );
 
uint8_t accel27_get_int1_pin ( accel27_t *ctx );
 
uint8_t accel27_get_int2_pin ( accel27_t *ctx );
 
err_t accel27_get_axes ( accel27_t *ctx, accel27_axes_t *axes );
 
err_t accel27_reset_device ( accel27_t *ctx );
 
#ifdef __cplusplus
}
#endif
#endif // ACCEL27_H
 
 // accel27
 
// ------------------------------------------------------------------------ END