adac2.h

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/****************************************************************************
** Copyright (C) 2020 MikroElektronika d.o.o.
** Contact: https://www.mikroe.com/contact
**
** Permission is hereby granted, free of charge, to any person obtaining a copy
** of this software and associated documentation files (the "Software"), to deal
** in the Software without restriction, including without limitation the rights
** to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
** copies of the Software, and to permit persons to whom the Software is
** furnished to do so, subject to the following conditions:
** The above copyright notice and this permission notice shall be
** included in all copies or substantial portions of the Software.
**
** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
**  USE OR OTHER DEALINGS IN THE SOFTWARE.
****************************************************************************/
 
#ifndef ADAC2_H
#define ADAC2_H
 
#ifdef __cplusplus
extern "C"{
#endif
 
#ifdef PREINIT_SUPPORTED
#include "preinit.h"
#endif
 
#ifdef MikroCCoreVersion
    #if MikroCCoreVersion >= 1
        #include "delays.h"
    #endif
#endif
 
#include "drv_digital_out.h"
#include "drv_digital_in.h"
#include "drv_spi_master.h"
#include "spi_specifics.h"
 
#define ADAC2_REG_GEN_PROD                  0x00
#define ADAC2_REG_GEN_REV                   0x01
#define ADAC2_REG_GEN_CNFG                  0x02
#define ADAC2_REG_GEN_CHNL_CTRL             0x03
#define ADAC2_REG_GEN_GPIO_CTRL             0x04
#define ADAC2_REG_GEN_GPI_INT               0x05
#define ADAC2_REG_GEN_GPI_DATA              0x06
#define ADAC2_REG_GEN_INT                   0x07
#define ADAC2_REG_GEN_INTEN                 0x08
#define ADAC2_REG_GEN_PWR_CTRL              0x09
#define ADAC2_REG_DCHNL_CMD                 0x20
#define ADAC2_REG_DCHNL_STA                 0x21
#define ADAC2_REG_DCHNL_CTRL1               0x22
#define ADAC2_REG_DCHNL_CTRL2               0x23
#define ADAC2_REG_DCHNL_DATA                0x24
#define ADAC2_REG_DCHNL_N_SEL               0x25
#define ADAC2_REG_DCHNL_N_SOC               0x26
#define ADAC2_REG_DCHNL_N_SGC               0x27
#define ADAC2_REG_AO_DATA_WR                0x40
#define ADAC2_REG_AO_OFFSET_CORR_WR         0x41
#define ADAC2_REG_AO_GAIN_CORR_WR           0x42
#define ADAC2_REG_AO_CNFG_WR                0x43
#define ADAC2_REG_AO_DATA_RD                0x44
#define ADAC2_REG_AO_OFFSET_CORR_RD         0x45
#define ADAC2_REG_AO_GAIN_CORR_RD           0x46
#define ADAC2_REG_AO_STA_RD                 0x47
 
 // adac2_reg
 
#define ADAC2_PRODUCT_ID                    0x2D
 
#define ADAC2_GEN_CNFG_CRC_EN_DISABLE       0x000000ul
#define ADAC2_GEN_CNFG_CRC_EN_ENABLE        0x800000ul
#define ADAC2_GEN_CNFG_CRC_EN_MASK          0x800000ul
#define ADAC2_GEN_CNFG_DACREF_SEL_INT       0x000000ul
#define ADAC2_GEN_CNFG_DACREF_SEL_EXT       0x400000ul
#define ADAC2_GEN_CNFG_DACREF_SEL_MASK      0x400000ul
#define ADAC2_GEN_CNFG_ADCREF_SEL_INT       0x000000ul
#define ADAC2_GEN_CNFG_ADCREF_SEL_EXT       0x200000ul
#define ADAC2_GEN_CNFG_ADCREF_SEL_MASK      0x200000ul
#define ADAC2_GEN_CNFG_LINE_CNFG_OPEN       0x000000ul
#define ADAC2_GEN_CNFG_LINE_CNFG_CLOSED     0x100000ul
#define ADAC2_GEN_CNFG_LINE_CNFG_MASK       0x100000ul
#define ADAC2_GEN_CNFG_AO_CNFG_HIGH_Z       0x000000ul
#define ADAC2_GEN_CNFG_AO_CNFG_25V          0x010000ul
#define ADAC2_GEN_CNFG_AO_CNFG_12p5V        0x020000ul
#define ADAC2_GEN_CNFG_AO_CNFG_25mA         0x060000ul
#define ADAC2_GEN_CNFG_AO_CNFG_12p5mA       0x080000ul
#define ADAC2_GEN_CNFG_AO_CNFG_MASK         0x0F0000ul
#define ADAC2_GEN_CNFG_AI1_2_CNFG_BOTH_PD   0x000000ul
#define ADAC2_GEN_CNFG_AI1_2_CNFG_AI1_SE    0x002000ul
#define ADAC2_GEN_CNFG_AI1_2_CNFG_AI2_SE    0x004000ul
#define ADAC2_GEN_CNFG_AI1_2_CNFG_BOTH_SE   0x006000ul
#define ADAC2_GEN_CNFG_AI1_2_CNFG_DIFF      0x008000ul
#define ADAC2_GEN_CNFG_AI1_2_CNFG_MASK      0x00E000ul
#define ADAC2_GEN_CNFG_AI3_CNFG_PD          0x000000ul
#define ADAC2_GEN_CNFG_AI3_CNFG_SE          0x001000ul
#define ADAC2_GEN_CNFG_AI3_CNFG_MASK        0x001000ul
#define ADAC2_GEN_CNFG_AI4_CNFG_PD          0x000000ul
#define ADAC2_GEN_CNFG_AI4_CNFG_SE          0x000800ul
#define ADAC2_GEN_CNFG_AI4_CNFG_MASK        0x000800ul
#define ADAC2_GEN_CNFG_AI5_6_CNFG_PD        0x000000ul
#define ADAC2_GEN_CNFG_AI5_6_CNFG_DIFF      0x000400ul
#define ADAC2_GEN_CNFG_AI5_6_CNFG_MASK      0x000700ul
#define ADAC2_GEN_CNFG_AI5_DF_GAIN_12p5V    0x000000ul
#define ADAC2_GEN_CNFG_AI5_DF_GAIN_0p5V     0x000040ul
#define ADAC2_GEN_CNFG_AI5_DF_GAIN_0p25V    0x000080ul
#define ADAC2_GEN_CNFG_AI5_DF_GAIN_0p125V   0x0000C0ul
#define ADAC2_GEN_CNFG_AI5_DF_GAIN_MASK     0x0000C0ul
#define ADAC2_GEN_CNFG_OVC_CTRL_AUTO        0x000000ul
#define ADAC2_GEN_CNFG_OVC_CTRL_HOST        0x000008ul
#define ADAC2_GEN_CNFG_OVC_CTRL_MASK        0x000008ul
 
#define ADAC2_ADC_DATA_RESOLUTION           0x7FFFFFul
#define ADAC2_DAC_DATA_RESOLUTION           0x03FFFFul
#define ADAC2_DAC_MIN_VALUE                 -131072l
#define ADAC2_DAC_MAX_VALUE                 131071l
#define ADAC2_FULL_SCALE_RANGE_25V          25.0f
#define ADAC2_FULL_SCALE_RANGE_12p5V        12.5f
#define ADAC2_FULL_SCALE_RANGE_2p5V         2.5f
#define ADAC2_FULL_SCALE_RANGE_0p5V         0.5f
#define ADAC2_FULL_SCALE_RANGE_0p25V        0.25f
#define ADAC2_FULL_SCALE_RANGE_0p125V       0.125f
 
#define ADAC2_START_CONVERSION              0x30
#define ADAC2_STOP_CONVERSION               0x10
#define ADAC2_DATA_RATE_5_SPS               0x00
#define ADAC2_DATA_RATE_10_SPS              0x01
#define ADAC2_DATA_RATE_15_SPS              0x02
#define ADAC2_DATA_RATE_30_SPS              0x03
#define ADAC2_DATA_RATE_50_SPS              0x04
#define ADAC2_DATA_RATE_60_SPS              0x05
#define ADAC2_DATA_RATE_225_SPS             0x06
#define ADAC2_DATA_RATE_450_SPS             0x07
#define ADAC2_DATA_RATE_900_SPS             0x08
#define ADAC2_DATA_RATE_1800_SPS            0x09
#define ADAC2_DATA_RATE_3600_SPS            0x0A
#define ADAC2_DATA_RATE_7200_SPS            0x0B
#define ADAC2_DATA_RATE_14400_SPS           0x0C
#define ADAC2_DATA_RATE_28800_SPS           0x0D
#define ADAC2_DATA_RATE_57600_SPS           0x0E
#define ADAC2_DATA_RATE_115200_SPS          0x0F
 
#define ADAC2_PD_STATE_STANDBY              0x00
#define ADAC2_PD_STATE_RESET                0x10
#define ADAC2_CONV_MODE_CONTINUOUS          0x00
#define ADAC2_CONV_MODE_SINGLE_CYCLE        0x02
#define ADAC2_CONV_MODE_CONT_SINGLE_CYCLE   0x03
 
#define ADAC2_CH_NONE                       0x00
#define ADAC2_CH_AI1_SINGLE_ENDED           0x01
#define ADAC2_CH_AI2_SINGLE_ENDED           0x02
#define ADAC2_CH_AI1_AI2_DIFFERENTIAL       0x03
#define ADAC2_CH_AI3_SINGLE_ENDED           0x04
#define ADAC2_CH_AI4_SINGLE_ENDED           0x05
#define ADAC2_CH_AI3_AI4_DIFFERENTIAL       0x06
#define ADAC2_CH_AI5_AI6_DIFFERENTIAL_25V   0x09
#define ADAC2_CH_AI5_AI6_DIFFERENTIAL_2p5V  0x0C
#define ADAC2_CH_AUX1_SINGLE_ENDED          0x0D
#define ADAC2_CH_AUX2_SINGLE_ENDED          0x0E
#define ADAC2_CH_AUX1_AUX2_DIFFERENTIAL     0x0F
#define ADAC2_CH_MASK                       0x000F00ul
 
#define ADAC2_GPIO_0_MASK                   0x01
#define ADAC2_GPIO_1_MASK                   0x02
#define ADAC2_GPIO_2_MASK                   0x04
#define ADAC2_GPIO_3_MASK                   0x08
#define ADAC2_GPIO_4_MASK                   0x10
#define ADAC2_GPIO_5_MASK                   0x20
#define ADAC2_GPIO_ALL_MASK                 0x3F
 
#define ADAC2_SET_DATA_SAMPLE_EDGE          SET_SPI_DATA_SAMPLE_EDGE
#define ADAC2_SET_DATA_SAMPLE_MIDDLE        SET_SPI_DATA_SAMPLE_MIDDLE
 
 // adac2_set
 
#define ADAC2_MAP_MIKROBUS( cfg, mikrobus ) \
    cfg.miso = MIKROBUS( mikrobus, MIKROBUS_MISO ); \
    cfg.mosi = MIKROBUS( mikrobus, MIKROBUS_MOSI ); \
    cfg.sck  = MIKROBUS( mikrobus, MIKROBUS_SCK ); \
    cfg.cs   = MIKROBUS( mikrobus, MIKROBUS_CS ); \
    cfg.rdy = MIKROBUS( mikrobus, MIKROBUS_AN ); \
    cfg.rst = MIKROBUS( mikrobus, MIKROBUS_RST ); \
    cfg.int_pin = MIKROBUS( mikrobus, MIKROBUS_INT )
 
 // adac2_map
 // adac2
 
typedef struct
{
    // Output pins
    digital_out_t rst;          
    // Input pins
    digital_in_t rdy;           
    digital_in_t int_pin;       
    // Modules
    spi_master_t spi;           
    pin_name_t   chip_select;   
    bool spi_crc_enable;        
} adac2_t;
 
typedef struct
{
    // Communication gpio pins
    pin_name_t miso;            
    pin_name_t mosi;            
    pin_name_t sck;             
    pin_name_t cs;              
    // Additional gpio pins
    pin_name_t rdy;             
    pin_name_t rst;             
    pin_name_t int_pin;         
    // static variable
    uint32_t                          spi_speed;    
    spi_master_mode_t                 spi_mode;     
    spi_master_chip_select_polarity_t cs_polarity;  
} adac2_cfg_t;
 
typedef enum
{
    ADAC2_OK = 0,
    ADAC2_ERROR = -1
 
} adac2_return_value_t;
 
void adac2_cfg_setup ( adac2_cfg_t *cfg );
 
err_t adac2_init ( adac2_t *ctx, adac2_cfg_t *cfg );
 
err_t adac2_default_cfg ( adac2_t *ctx );
 
err_t adac2_write_register ( adac2_t *ctx, uint8_t reg, uint32_t data_in );
 
err_t adac2_read_register ( adac2_t *ctx, uint8_t reg, uint32_t *data_out );
 
err_t adac2_enable_spi_crc ( adac2_t *ctx );
 
err_t adac2_disable_spi_crc ( adac2_t *ctx );
 
err_t adac2_check_communication ( adac2_t *ctx );
 
void adac2_reset_device ( adac2_t *ctx );
 
uint8_t adac2_get_rdy_pin ( adac2_t *ctx );
 
uint8_t adac2_get_int_pin ( adac2_t *ctx );
 
err_t adac2_start_conversion ( adac2_t *ctx, uint8_t data_rate );
 
err_t adac2_stop_conversion ( adac2_t *ctx );
 
err_t adac2_set_conversion_mode ( adac2_t *ctx, uint8_t mode );
 
err_t adac2_set_active_ain_channel ( adac2_t *ctx, uint8_t channel );
 
err_t adac2_read_raw_adc ( adac2_t *ctx, int32_t *raw_adc );
 
err_t adac2_read_voltage ( adac2_t *ctx, float fsr, float *voltage );
 
err_t adac2_write_dac ( adac2_t *ctx, int32_t dac );
 
#ifdef __cplusplus
}
#endif
#endif // ADAC2_H
 
 // adac2
 
// ------------------------------------------------------------------------ END