adc13 2.0.0.0
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Settings for registers of ADC 13 Click driver. More...
Settings for registers of ADC 13 Click driver.
#define ADC13_CHECKSUM_CONSTANT 0x9B |
Checksum constant.
Checksum constant definition.
#define ADC13_GPIO0 0x01 |
ADC 13 GPIO pin high setting.
Specified setting for GPIO pins of ADC 13 Click driver.
#define ADC13_GPIO1 0x02 |
#define ADC13_GPIO2 0x04 |
#define ADC13_GPIO3 0x08 |
#define ADC13_GPIO4 0x10 |
#define ADC13_GPIO5 0x20 |
#define ADC13_GPIO6 0x40 |
#define ADC13_GPIO7 0x80 |
#define ADC13_ID_DEV_MASK 0xE0 |
ADC 13 register mask summary.
The list of register masks.
#define ADC13_ID_REV_MASK 0x1F |
#define ADC13_IDACMAG_MAG1_1000uA 6 |
#define ADC13_IDACMAG_MAG1_100uA 2 |
#define ADC13_IDACMAG_MAG1_1500uA 7 |
#define ADC13_IDACMAG_MAG1_2000uA 8 |
#define ADC13_IDACMAG_MAG1_2500uA 9 |
#define ADC13_IDACMAG_MAG1_250uA 3 |
#define ADC13_IDACMAG_MAG1_3000uA 10 |
#define ADC13_IDACMAG_MAG1_500uA 4 |
#define ADC13_IDACMAG_MAG1_50uA 1 |
#define ADC13_IDACMAG_MAG1_750uA 5 |
#define ADC13_IDACMAG_MAG1_MASK 0x0F |
#define ADC13_IDACMAG_MAG1_OFF 0 |
#define ADC13_IDACMAG_MAG2_1000uA 6 |
#define ADC13_IDACMAG_MAG2_100uA 2 |
#define ADC13_IDACMAG_MAG2_1500uA 7 |
#define ADC13_IDACMAG_MAG2_2000uA 8 |
#define ADC13_IDACMAG_MAG2_2500uA 9 |
#define ADC13_IDACMAG_MAG2_250uA 3 |
#define ADC13_IDACMAG_MAG2_3000uA 10 |
#define ADC13_IDACMAG_MAG2_500uA 4 |
#define ADC13_IDACMAG_MAG2_50uA 1 |
#define ADC13_IDACMAG_MAG2_750uA 5 |
#define ADC13_IDACMAG_MAG2_MASK 0xF0 |
#define ADC13_IDACMAG_MAG2_OFF 0 |
ADC 13 IDACMAG register setting.
Specified setting for IDACMAG register of ADC 13 Click driver.
#define ADC13_IDACMUX_MUX1_AIN0 0 |
#define ADC13_IDACMUX_MUX1_AIN1 1 |
#define ADC13_IDACMUX_MUX1_AIN2 2 |
#define ADC13_IDACMUX_MUX1_AIN3 3 |
#define ADC13_IDACMUX_MUX1_AIN4 4 |
#define ADC13_IDACMUX_MUX1_AIN5 5 |
#define ADC13_IDACMUX_MUX1_AIN6 6 |
#define ADC13_IDACMUX_MUX1_AIN7 7 |
#define ADC13_IDACMUX_MUX1_AIN8 8 |
#define ADC13_IDACMUX_MUX1_AIN9 9 |
#define ADC13_IDACMUX_MUX1_AINCOM 10 |
#define ADC13_IDACMUX_MUX1_MASK 0x0F |
#define ADC13_IDACMUX_MUX1_NO_CONNECTION 11 |
#define ADC13_IDACMUX_MUX2_AIN0 0 |
ADC 13 IDACMUX register setting.
Specified setting for IDACMUX register of ADC 13 Click driver.
#define ADC13_IDACMUX_MUX2_AIN1 1 |
#define ADC13_IDACMUX_MUX2_AIN2 2 |
#define ADC13_IDACMUX_MUX2_AIN3 3 |
#define ADC13_IDACMUX_MUX2_AIN4 4 |
#define ADC13_IDACMUX_MUX2_AIN5 5 |
#define ADC13_IDACMUX_MUX2_AIN6 6 |
#define ADC13_IDACMUX_MUX2_AIN7 7 |
#define ADC13_IDACMUX_MUX2_AIN8 8 |
#define ADC13_IDACMUX_MUX2_AIN9 9 |
#define ADC13_IDACMUX_MUX2_AINCOM 10 |
#define ADC13_IDACMUX_MUX2_MASK 0xF0 |
#define ADC13_IDACMUX_MUX2_NO_CONNECTION 11 |
#define ADC13_INPMUX_MUXN_AIN0 0 |
#define ADC13_INPMUX_MUXN_AIN1 1 |
#define ADC13_INPMUX_MUXN_AIN2 2 |
#define ADC13_INPMUX_MUXN_AIN3 3 |
#define ADC13_INPMUX_MUXN_AIN4 4 |
#define ADC13_INPMUX_MUXN_AIN5 5 |
#define ADC13_INPMUX_MUXN_AIN6 6 |
#define ADC13_INPMUX_MUXN_AIN7 7 |
#define ADC13_INPMUX_MUXN_AIN8 8 |
#define ADC13_INPMUX_MUXN_AIN9 9 |
#define ADC13_INPMUX_MUXN_AINCOM 10 |
#define ADC13_INPMUX_MUXN_AN_POW_SUPP_NEG 12 |
#define ADC13_INPMUX_MUXN_DIG_POW_SUPP_NEG 13 |
#define ADC13_INPMUX_MUXN_FLOAT 15 |
#define ADC13_INPMUX_MUXN_MASK 0x0F |
#define ADC13_INPMUX_MUXN_TDAC_NEG 14 |
#define ADC13_INPMUX_MUXN_TEMP_SENSOR_NEG 11 |
#define ADC13_INPMUX_MUXP_AIN0 0 |
ADC 13 INPMUX register setting.
Specified setting for INPMUX register of ADC 13 Click driver.
#define ADC13_INPMUX_MUXP_AIN1 1 |
#define ADC13_INPMUX_MUXP_AIN2 2 |
#define ADC13_INPMUX_MUXP_AIN3 3 |
#define ADC13_INPMUX_MUXP_AIN4 4 |
#define ADC13_INPMUX_MUXP_AIN5 5 |
#define ADC13_INPMUX_MUXP_AIN6 6 |
#define ADC13_INPMUX_MUXP_AIN7 7 |
#define ADC13_INPMUX_MUXP_AIN8 8 |
#define ADC13_INPMUX_MUXP_AIN9 9 |
#define ADC13_INPMUX_MUXP_AINCOM 10 |
#define ADC13_INPMUX_MUXP_AN_POW_SUPP_POS 12 |
#define ADC13_INPMUX_MUXP_DIG_POW_SUPP_POS 13 |
#define ADC13_INPMUX_MUXP_FLOAT 15 |
#define ADC13_INPMUX_MUXP_MASK 0xF0 |
#define ADC13_INPMUX_MUXP_TDAC_POS 14 |
#define ADC13_INPMUX_MUXP_TEMP_SENSOR_POS 11 |
#define ADC13_INTERFACE_CRC_DISABLE 0 |
#define ADC13_INTERFACE_CRC_ENABLE_CHECKSUM 1 |
#define ADC13_INTERFACE_CRC_ENABLE_CRC 2 |
#define ADC13_INTERFACE_CRC_MASK 0x03 |
#define ADC13_INTERFACE_STATUS_DISABLE 0 |
#define ADC13_INTERFACE_STATUS_ENABLE 1 |
#define ADC13_INTERFACE_STATUS_MASK 0x04 |
#define ADC13_INTERFACE_TIMEOUT_DISABLE 0 |
ADC 13 INTERFACE register setting.
Specified setting for INTERFACE register of ADC 13 Click driver.
#define ADC13_INTERFACE_TIMEOUT_ENABLE 1 |
#define ADC13_INTERFACE_TIMEOUT_MASK 0x08 |
#define ADC13_MODE0_CHOP_AND_IDAC_ENABLE 3 |
#define ADC13_MODE0_CHOP_DISABLE 0 |
#define ADC13_MODE0_CHOP_ENABLE 1 |
#define ADC13_MODE0_CHOP_IDAC_ENABLE 2 |
#define ADC13_MODE0_CHOP_MASK 0x30 |
#define ADC13_MODE0_DELAY_139uS 5 |
#define ADC13_MODE0_DELAY_17uS 2 |
#define ADC13_MODE0_DELAY_1p1mS 8 |
#define ADC13_MODE0_DELAY_278uS 6 |
#define ADC13_MODE0_DELAY_2p2mS 9 |
#define ADC13_MODE0_DELAY_35uS 3 |
#define ADC13_MODE0_DELAY_4p4mS 10 |
#define ADC13_MODE0_DELAY_555uS 7 |
#define ADC13_MODE0_DELAY_69uS 4 |
#define ADC13_MODE0_DELAY_8p7uS 1 |
#define ADC13_MODE0_DELAY_8p8mS 11 |
#define ADC13_MODE0_DELAY_MASK 0x0F |
#define ADC13_MODE0_DELAY_NO_DELAY 0 |
#define ADC13_MODE0_REFREV_MASK 0x80 |
#define ADC13_MODE0_REFREV_NORMAL 0 |
ADC 13 MODE0 register setting.
Specified setting for MODE0 register of ADC 13 Click driver.
#define ADC13_MODE0_REFREV_REVERSE 1 |
#define ADC13_MODE0_RUN_MODE_CONTINUOUS 0 |
#define ADC13_MODE0_RUN_MODE_MASK 0x40 |
#define ADC13_MODE0_RUN_MODE_ONE_SHOT 1 |
#define ADC13_MODE1_FILTER_FIR_MODE 4 |
#define ADC13_MODE1_FILTER_MASK 0xE0 |
#define ADC13_MODE1_FILTER_SINC1_MODE 0 |
ADC 13 MODE1 register setting.
Specified setting for MODE1 register of ADC 13 Click driver.
#define ADC13_MODE1_FILTER_SINC2_MODE 1 |
#define ADC13_MODE1_FILTER_SINC3_MODE 2 |
#define ADC13_MODE1_FILTER_SINC4_MODE 3 |
#define ADC13_MODE1_SBADC_ADC1_OUT 0 |
#define ADC13_MODE1_SBADC_ADC2_OUT 1 |
#define ADC13_MODE1_SBADC_MASK 0x10 |
#define ADC13_MODE1_SBMAG_0p5uA_CURR 1 |
#define ADC13_MODE1_SBMAG_10MOHM_RES 6 |
#define ADC13_MODE1_SBMAG_10uA_CURR 3 |
#define ADC13_MODE1_SBMAG_200uA_CURR 5 |
#define ADC13_MODE1_SBMAG_2uA_CURR 2 |
#define ADC13_MODE1_SBMAG_50uA_CURR 4 |
#define ADC13_MODE1_SBMAG_MASK 0x07 |
#define ADC13_MODE1_SBMAG_NO_CURR_NO_RES 0 |
#define ADC13_MODE1_SBPOL_MASK 0x08 |
#define ADC13_MODE1_SBPOL_PULLDOWN_MODE 1 |
#define ADC13_MODE1_SBPOL_PULLUP_MODE 0 |
#define ADC13_MODE2_BYPASS_MASK 0x80 |
#define ADC13_MODE2_BYPASS_PGA_BYPASSED 1 |
#define ADC13_MODE2_BYPASS_PGA_ENABLED 0 |
ADC 13 MODE2 register setting.
Specified setting for MODE2 register of ADC 13 Click driver.
#define ADC13_MODE2_DR_100SPS 7 |
#define ADC13_MODE2_DR_10SPS 2 |
#define ADC13_MODE2_DR_1200SPS 9 |
#define ADC13_MODE2_DR_14400SPS 13 |
#define ADC13_MODE2_DR_16p6SPS 3 |
#define ADC13_MODE2_DR_19200SPS 14 |
#define ADC13_MODE2_DR_20SPS 4 |
#define ADC13_MODE2_DR_2400SPS 10 |
#define ADC13_MODE2_DR_2p5SPS 0 |
#define ADC13_MODE2_DR_38400SPS 15 |
#define ADC13_MODE2_DR_400SPS 8 |
#define ADC13_MODE2_DR_4800SPS 11 |
#define ADC13_MODE2_DR_50SPS 5 |
#define ADC13_MODE2_DR_5SPS 1 |
#define ADC13_MODE2_DR_60SPS 6 |
#define ADC13_MODE2_DR_7200SPS 12 |
#define ADC13_MODE2_DR_MASK 0x0F |
#define ADC13_MODE2_GAIN_1 0 |
#define ADC13_MODE2_GAIN_16 4 |
#define ADC13_MODE2_GAIN_2 1 |
#define ADC13_MODE2_GAIN_32 5 |
#define ADC13_MODE2_GAIN_4 2 |
#define ADC13_MODE2_GAIN_8 3 |
#define ADC13_MODE2_GAIN_MASK 0x70 |
#define ADC13_POWER_INTREF_DISABLE 0 |
#define ADC13_POWER_INTREF_ENABLE 1 |
#define ADC13_POWER_INTREF_MASK 0x01 |
#define ADC13_POWER_RESET_MASK 0x10 |
#define ADC13_POWER_RESET_NO_NEW_RESET 0 |
ADC 13 POWER register setting.
Specified setting for POWER register of ADC 13 Click driver.
#define ADC13_POWER_RESET_OCCURRED 1 |
#define ADC13_POWER_VBIAS_DISABLE 0 |
#define ADC13_POWER_VBIAS_ENABLE 1 |
#define ADC13_POWER_VBIAS_MASK 0x02 |
#define ADC13_REFMUX_RMUXN_EXT_AIN1 1 |
#define ADC13_REFMUX_RMUXN_EXT_AIN3 2 |
#define ADC13_REFMUX_RMUXN_EXT_AIN5 3 |
#define ADC13_REFMUX_RMUXN_INTERNAL 0 |
#define ADC13_REFMUX_RMUXN_INTERNAL_AVSS 4 |
#define ADC13_REFMUX_RMUXN_MASK 0x07 |
#define ADC13_REFMUX_RMUXP_EXT_AIN0 1 |
#define ADC13_REFMUX_RMUXP_EXT_AIN2 2 |
#define ADC13_REFMUX_RMUXP_EXT_AIN4 3 |
#define ADC13_REFMUX_RMUXP_INTERNAL 0 |
ADC 13 REFMUX register setting.
Specified setting for REFMUX register of ADC 13 Click driver.
#define ADC13_REFMUX_RMUXP_INTERNAL_AVDD 4 |
#define ADC13_REFMUX_RMUXP_MASK 0x38 |
#define ADC13_REG_COUNT_MASK 0x1F |
#define ADC13_SET_DATA_SAMPLE_EDGE SET_SPI_DATA_SAMPLE_EDGE |
Data sample selection.
This macro sets data samples for SPI modules.
#define ADC13_SET_DATA_SAMPLE_MIDDLE SET_SPI_DATA_SAMPLE_MIDDLE |
#define ADC13_STATUS_ADC1_NEW_DATA 0x40 |
#define ADC13_STATUS_ADC2_NEW_DATA 0x80 |
ADC 13 STATUS byte field bits.
Specified bits for STATUS byte field of ADC 13 Click driver.
#define ADC13_STATUS_EXTCLK_EXTERNAL 0x20 |
#define ADC13_STATUS_PGAD_ALM_DIFF_RANGE 0x02 |
#define ADC13_STATUS_PGAH_ALM_HIGH_VOLTAGE 0x04 |
#define ADC13_STATUS_PGAL_ALM_LOW_VOLTAGE 0x08 |
#define ADC13_STATUS_REF_ALM_LOW_REF 0x10 |
#define ADC13_STATUS_RESET_OCCURRED 0x01 |
#define ADC13_TDACN_MAGN_0p5V 25 |
#define ADC13_TDACN_MAGN_1p5V 24 |
#define ADC13_TDACN_MAGN_2p25V 22 |
#define ADC13_TDACN_MAGN_2p375V 21 |
#define ADC13_TDACN_MAGN_2p4375V 20 |
#define ADC13_TDACN_MAGN_2p46875V 19 |
#define ADC13_TDACN_MAGN_2p484375V 18 |
#define ADC13_TDACN_MAGN_2p4921875V 17 |
#define ADC13_TDACN_MAGN_2p5078125V 1 |
#define ADC13_TDACN_MAGN_2p515625V 2 |
#define ADC13_TDACN_MAGN_2p53125V 3 |
#define ADC13_TDACN_MAGN_2p5625V 4 |
#define ADC13_TDACN_MAGN_2p5V 0 |
#define ADC13_TDACN_MAGN_2p625V 5 |
#define ADC13_TDACN_MAGN_2p75V 6 |
#define ADC13_TDACN_MAGN_2V 23 |
#define ADC13_TDACN_MAGN_3p5V 8 |
#define ADC13_TDACN_MAGN_3V 7 |
#define ADC13_TDACN_MAGN_4p5V 9 |
#define ADC13_TDACN_MAGN_MASK 0x1F |
#define ADC13_TDACN_OUTN_AIN7 1 |
#define ADC13_TDACN_OUTN_MASK 0x80 |
#define ADC13_TDACN_OUTN_NO_CONNECTION 0 |
ADC 13 TDACN register setting.
Specified setting for TDACN register of ADC 13 Click driver.
#define ADC13_TDACP_MAGP_0p5V 25 |
#define ADC13_TDACP_MAGP_1p5V 24 |
#define ADC13_TDACP_MAGP_2p25V 22 |
#define ADC13_TDACP_MAGP_2p375V 21 |
#define ADC13_TDACP_MAGP_2p4375V 20 |
#define ADC13_TDACP_MAGP_2p46875V 19 |
#define ADC13_TDACP_MAGP_2p484375V 18 |
#define ADC13_TDACP_MAGP_2p4921875V 17 |
#define ADC13_TDACP_MAGP_2p5078125V 1 |
#define ADC13_TDACP_MAGP_2p515625V 2 |
#define ADC13_TDACP_MAGP_2p53125V 3 |
#define ADC13_TDACP_MAGP_2p5625V 4 |
#define ADC13_TDACP_MAGP_2p5V 0 |
#define ADC13_TDACP_MAGP_2p625V 5 |
#define ADC13_TDACP_MAGP_2p75V 6 |
#define ADC13_TDACP_MAGP_2V 23 |
#define ADC13_TDACP_MAGP_3p5V 8 |
#define ADC13_TDACP_MAGP_3V 7 |
#define ADC13_TDACP_MAGP_4p5V 9 |
#define ADC13_TDACP_MAGP_MASK 0x1F |
#define ADC13_TDACP_OUTP_AIN6 1 |
#define ADC13_TDACP_OUTP_MASK 0x80 |
#define ADC13_TDACP_OUTP_NO_CONNECTION 0 |
ADC 13 TDACP register setting.
Specified setting for TDACP register of ADC 13 Click driver.
#define ADC13_TEMP_COEFF 0.42 |
#define ADC13_TEMP_HEAT_OFFSET 0.7 |
#define ADC13_TEMP_MILIVOLTS 122.4 |
Temperature constant.
Temperature constants definition.
#define ADC13_TEMP_OFFSET 25.0 |
#define ADC13_TEMP_V_TO_MV 1000 |
#define ADC13_VREF_3V3 3.3 |
#define ADC13_VREF_5V 5 |
#define ADC13_VREF_INTERNAL 2.5 |
Voltage reference.
Voltage reference definition in voltages.
#define ADC13_VREF_INTERNAL_AVDD 5 |
#define GET_REG_BITS | ( | reg_data, | |
bit_mask ) ( ( reg_data & bit_mask ) >> GET_RIGHTMOST_SET_BIT( bit_mask ) ) |
Get reg bits macro.
Macro to get a desired bits of the reg_data variable.
#define GET_RIGHTMOST_SET_BIT | ( | bit_mask | ) |
Calculate position of rightmost set bit.
Macro which calculates and returns the position of the rightmost set bit.
#define SET_REG_BITS | ( | reg_data, | |
bit_mask, | |||
in_data ) |
Set reg bits macro.
Macro to set a desired bits of the reg_data variable.