adc20.h

Go to the documentation of this file.

/****************************************************************************
** Copyright (C) 2020 MikroElektronika d.o.o.
** Contact: https://www.mikroe.com/contact
**
** Permission is hereby granted, free of charge, to any person obtaining a copy
** of this software and associated documentation files (the "Software"), to deal
** in the Software without restriction, including without limitation the rights
** to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
** copies of the Software, and to permit persons to whom the Software is
** furnished to do so, subject to the following conditions:
** The above copyright notice and this permission notice shall be
** included in all copies or substantial portions of the Software.
**
** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
**  USE OR OTHER DEALINGS IN THE SOFTWARE.
****************************************************************************/
 
#ifndef ADC20_H
#define ADC20_H
 
#ifdef __cplusplus
extern "C"{
#endif
 
#ifdef PREINIT_SUPPORTED
#include "preinit.h"
#endif
 
#ifdef MikroCCoreVersion
    #if MikroCCoreVersion >= 1
        #include "delays.h"
    #endif
#endif
 
#include "drv_digital_out.h"
#include "drv_digital_in.h"
#include "drv_spi_master.h"
#include "spi_specifics.h"
 
#define ADC20_CMD_NOP                       0x00
#define ADC20_CMD_REG_READ                  0x10
#define ADC20_CMD_REG_WRITE                 0x08
#define ADC20_CMD_SET_BIT                   0x18
#define ADC20_CMD_CLEAR_BIT                 0x20
 
#define ADC20_REG_SYSTEM_STATUS             0x00
#define ADC20_REG_GENERAL_CFG               0x01
#define ADC20_REG_DATA_CFG                  0x02
#define ADC20_REG_OSR_CFG                   0x03
#define ADC20_REG_OPMODE_CFG                0x04
#define ADC20_REG_PIN_CFG                   0x05
#define ADC20_REG_GPIO_CFG                  0x07
#define ADC20_REG_GPO_DRIVE_CFG             0x09
#define ADC20_REG_GPO_VALUE                 0x0B
#define ADC20_REG_GPI_VALUE                 0x0D
#define ADC20_REG_SEQUENCE_CFG              0x10
#define ADC20_REG_CHANNEL_SEL               0x11
#define ADC20_REG_AUTO_SEQ_CH_SEL           0x12
 
 // adc20_reg
 
#define ADC20_DATA_CFG_FIX_PAT              0x80
#define ADC20_DATA_CFG_APPEND_CHANNEL_ID    0x10
#define ADC20_DATA_CFG_SPI_MODE_0           0x00
#define ADC20_DATA_CFG_SPI_MODE_1           0x01
#define ADC20_DATA_CFG_SPI_MODE_2           0x02
#define ADC20_DATA_CFG_SPI_MODE_3           0x03
#define ADC20_DATA_CFG_SPI_MODE_MASK        0x03
 
#define ADC20_FIXED_CODE                    0xA5A0
 
#define ADC20_CHANNEL_0                     0x01
#define ADC20_CHANNEL_1                     0x02
#define ADC20_CHANNEL_2                     0x04
#define ADC20_CHANNEL_3                     0x08
#define ADC20_CHANNEL_4                     0x10
#define ADC20_CHANNEL_5                     0x20
#define ADC20_CHANNEL_6                     0x40
#define ADC20_CHANNEL_7                     0x80
#define ADC20_CHANNEL_NONE                  0x00
#define ADC20_CHANNEL_MASK                  0xFF
 
#define ADC20_CHANNEL_ID_0                  0
#define ADC20_CHANNEL_ID_1                  1
#define ADC20_CHANNEL_ID_2                  2
#define ADC20_CHANNEL_ID_3                  3
#define ADC20_CHANNEL_ID_4                  4
#define ADC20_CHANNEL_ID_5                  5
#define ADC20_CHANNEL_ID_6                  6
#define ADC20_CHANNEL_ID_7                  7
#define ADC20_CHANNEL_ID_MASK               0x0F
 
#define ADC20_PIN_CFG_ANALOG                0
#define ADC20_PIN_CFG_GPIO                  1
 
#define ADC20_GPIO_CFG_DIG_INPUT            0
#define ADC20_GPIO_CFG_DIG_OUTPUT           1
 
#define ADC20_GPO_DRIVE_CFG_OPEN_DRAIN      0
#define ADC20_GPO_DRIVE_CFG_PUSH_PULL       1
 
#define ADC20_GPIO_VALUE_LOW                0
#define ADC20_GPIO_VALUE_HIGH               1
 
#define ADC20_OSR_NO_AVERAGING              0x00
#define ADC20_OSR_2_SAMPLES                 0x01
#define ADC20_OSR_4_SAMPLES                 0x02
#define ADC20_OSR_8_SAMPLES                 0x03
#define ADC20_OSR_16_SAMPLES                0x04
#define ADC20_OSR_32_SAMPLES                0x05
#define ADC20_OSR_64_SAMPLES                0x06
#define ADC20_OSR_128_SAMPLES               0x07
#define ADC20_OSR_MASK                      0x07
 
#define ADC20_SEQ_STOP                      0x00
#define ADC20_SEQ_START                     0x10
#define ADC20_SEQ_MODE_MANUAL               0x00
#define ADC20_SEQ_MODE_AUTO                 0x01
#define ADC20_SEQ_MODE_OTF                  0x02
#define ADC20_SEQ_MODE_MASK                 0x03
 
#define ADC20_ADC_OFFSET                    4
#define ADC20_RES_12BIT                     0x0FFF
#define ADC20_VREF_3V3                      3.3f
 
#define ADC20_SET_DATA_SAMPLE_EDGE          SET_SPI_DATA_SAMPLE_EDGE
#define ADC20_SET_DATA_SAMPLE_MIDDLE        SET_SPI_DATA_SAMPLE_MIDDLE
 
 // adc20_set
 
#define ADC20_MAP_MIKROBUS( cfg, mikrobus ) \
    cfg.miso = MIKROBUS( mikrobus, MIKROBUS_MISO ); \
    cfg.mosi = MIKROBUS( mikrobus, MIKROBUS_MOSI ); \
    cfg.sck  = MIKROBUS( mikrobus, MIKROBUS_SCK ); \
    cfg.cs   = MIKROBUS( mikrobus, MIKROBUS_CS );
 
 // adc20_map
 // adc20
 
typedef struct
{
    // Modules
    spi_master_t spi;                   
    pin_name_t   chip_select;           
} adc20_t;
 
typedef struct
{
    // Communication gpio pins
    pin_name_t miso;                    
    pin_name_t mosi;                    
    pin_name_t sck;                     
    pin_name_t cs;                      
    // static variable
    uint32_t                          spi_speed;    
    spi_master_mode_t                 spi_mode;     
    spi_master_chip_select_polarity_t cs_polarity;  
} adc20_cfg_t;
 
typedef enum
{
    ADC20_OK = 0,
    ADC20_ERROR = -1
 
} adc20_return_value_t;
 
void adc20_cfg_setup ( adc20_cfg_t *cfg );
 
err_t adc20_init ( adc20_t *ctx, adc20_cfg_t *cfg );
 
err_t adc20_default_cfg ( adc20_t *ctx );
 
err_t adc20_write_register ( adc20_t *ctx, uint8_t reg, uint8_t data_in );
 
err_t adc20_read_register ( adc20_t *ctx, uint8_t reg, uint8_t *data_out );
 
err_t adc20_read_data ( adc20_t *ctx, uint16_t *data_out );
 
err_t adc20_check_communication ( adc20_t *ctx );
 
err_t adc20_start_auto_sequence ( adc20_t *ctx );
 
err_t adc20_stop_auto_sequence ( adc20_t *ctx );
 
err_t adc20_set_pin_config ( adc20_t *ctx, uint8_t ch_mask, uint8_t pin_cfg );
 
err_t adc20_set_gpio_config ( adc20_t *ctx, uint8_t ch_mask, uint8_t gpio_cfg );
 
err_t adc20_set_gpo_drive_config ( adc20_t *ctx, uint8_t ch_mask, uint8_t gpo_drive_cfg );
 
err_t adc20_set_gpo_value ( adc20_t *ctx, uint8_t ch_mask, uint8_t value );
 
err_t adc20_read_gpio_value ( adc20_t *ctx, uint8_t *gpio_value );
 
#ifdef __cplusplus
}
#endif
#endif // ADC20_H
 
 // adc20
 
// ------------------------------------------------------------------------ END