Settings for registers of 3D Hall 10 Click driver. More...

Macros
#define	C3DHALL10_CONV_AVG_1X 0x0000
	3D Hall 10 device config register settings.

#define	C3DHALL10_CONV_AVG_2X 0x1000

#define	C3DHALL10_CONV_AVG_4X 0x2000

#define	C3DHALL10_CONV_AVG_8X 0x3000

#define	C3DHALL10_CONV_AVG_16X 0x4000

#define	C3DHALL10_CONV_AVG_32X 0x5000

#define	C3DHALL10_CONV_AVG_BIT_MASK 0x7000

#define	C3DHALL10_MAG_TEMPCO_0 0x0000

#define	C3DHALL10_MAG_TEMPCO_0p12 0x0100

#define	C3DHALL10_MAG_TEMPCO_0p03 0x0200

#define	C3DHALL10_MAG_TEMPCO_0p2 0x0300

#define	C3DHALL10_MAG_TEMPCO_BIT_MASK 0x0300

#define	C3DHALL10_OPERATING_MODE_CONFIG 0x0000

#define	C3DHALL10_OPERATING_MODE_STANDBY 0x0010

#define	C3DHALL10_OPERATING_MODE_MEASURE 0x0020

#define	C3DHALL10_OPERATING_MODE_TRIGGER 0x0030

#define	C3DHALL10_OPERATING_MODE_DUTY_CYCLED 0x0040

#define	C3DHALL10_OPERATING_MODE_SLEEP 0x0050

#define	C3DHALL10_OPERATING_MODE_DEEP_SLEEP 0x0060

#define	C3DHALL10_OPERATING_MODE_BIT_MASK 0x0070

#define	C3DHALL10_T_CH_EN_DISABLE 0x0000

#define	C3DHALL10_T_CH_EN_ENABLE 0x0008

#define	C3DHALL10_T_CH_EN_BIT_MASK 0x0008

#define	C3DHALL10_T_RATE_PER_CONV_AVG 0x0000

#define	C3DHALL10_T_RATE_ONCE_PER_CONV 0x0004

#define	C3DHALL10_T_RATE_BIT_MASK 0x0004

#define	C3DHALL10_T_HLT_EN_DISABLE 0x0000

#define	C3DHALL10_T_HLT_EN_ENABLE 0x0002

#define	C3DHALL10_T_HLT_EN_BIT_MASK 0x0002

#define	C3DHALL10_ANGLE_EN_NO_ANGLE 0x0000
	3D Hall 10 sensor config register settings.

#define	C3DHALL10_ANGLE_EN_XY_ANGLE 0x4000

#define	C3DHALL10_ANGLE_EN_YZ_ANGLE 0x8000

#define	C3DHALL10_ANGLE_EN_XZ_ANGLE 0xC000

#define	C3DHALL10_ANGLE_EN_BIT_MASK 0xC000

#define	C3DHALL10_SLEEPTIME_1MS 0x0000

#define	C3DHALL10_SLEEPTIME_5MS 0x0400

#define	C3DHALL10_SLEEPTIME_10MS 0x0800

#define	C3DHALL10_SLEEPTIME_15MS 0x0C00

#define	C3DHALL10_SLEEPTIME_20MS 0x1000

#define	C3DHALL10_SLEEPTIME_30MS 0x1400

#define	C3DHALL10_SLEEPTIME_50MS 0x1800

#define	C3DHALL10_SLEEPTIME_100MS 0x1C00

#define	C3DHALL10_SLEEPTIME_500MS 0x2000

#define	C3DHALL10_SLEEPTIME_1000MS 0x2400

#define	C3DHALL10_SLEEPTIME_BIT_MASK 0x3C00

#define	C3DHALL10_MAG_CH_EN_DISABLE 0x0000

#define	C3DHALL10_MAG_CH_EN_ENABLE_X 0x0040

#define	C3DHALL10_MAG_CH_EN_ENABLE_Y 0x0080

#define	C3DHALL10_MAG_CH_EN_ENABLE_XY 0x00C0

#define	C3DHALL10_MAG_CH_EN_ENABLE_Z 0x0100

#define	C3DHALL10_MAG_CH_EN_ENABLE_ZX 0x0140

#define	C3DHALL10_MAG_CH_EN_ENABLE_YZ 0x0180

#define	C3DHALL10_MAG_CH_EN_ENABLE_XYZ 0x01C0

#define	C3DHALL10_MAG_CH_EN_ENABLE_XYX 0x0200

#define	C3DHALL10_MAG_CH_EN_ENABLE_YXY 0x0240

#define	C3DHALL10_MAG_CH_EN_ENABLE_YZY 0x0280

#define	C3DHALL10_MAG_CH_EN_ENABLE_ZYZ 0x02C0

#define	C3DHALL10_MAG_CH_EN_ENABLE_ZXZ 0x0300

#define	C3DHALL10_MAG_CH_EN_ENABLE_XZX 0x0340

#define	C3DHALL10_MAG_CH_EN_ENABLE_XYZYX 0x0380

#define	C3DHALL10_MAG_CH_EN_ENABLE_XYZZYX 0x03C0

#define	C3DHALL10_MAG_CH_EN_BIT_MASK 0x03C0

#define	C3DHALL10_Z_RANGE_50mT 0x0000

#define	C3DHALL10_Z_RANGE_25mT 0x0010

#define	C3DHALL10_Z_RANGE_100mT 0x0020

#define	C3DHALL10_Z_RANGE_BIT_MASK 0x0030

#define	C3DHALL10_Y_RANGE_50mT 0x0000

#define	C3DHALL10_Y_RANGE_25mT 0x0004

#define	C3DHALL10_Y_RANGE_100mT 0x0008

#define	C3DHALL10_Y_RANGE_BIT_MASK 0x000C

#define	C3DHALL10_X_RANGE_50mT 0x0000

#define	C3DHALL10_X_RANGE_25mT 0x0001

#define	C3DHALL10_X_RANGE_100mT 0x0002

#define	C3DHALL10_X_RANGE_BIT_MASK 0x0003

#define	C3DHALL10_DIAG_SEL_ALL_DP_DIAG_ALL 0x0000
	3D Hall 10 system config register settings.

#define	C3DHALL10_DIAG_SEL_EN_DP_ONLY_DIAG_ALL 0x1000

#define	C3DHALL10_DIAG_SEL_ALL_DP_DIAG_SEQ 0x2000

#define	C3DHALL10_DIAG_SEL_EN_DP_ONLY_DIAG_SEQ 0x3000

#define	C3DHALL10_DIAG_SEL_BIT_MASK 0x3000

#define	C3DHALL10_TRIGGER_MODE_SPI_CMD 0x0000

#define	C3DHALL10_TRIGGER_MODE_CS_PULSE 0x0200

#define	C3DHALL10_TRIGGER_MODE_ALERT_PULSE 0x0400

#define	C3DHALL10_TRIGGER_MODE_BIT_MASK 0x0600

#define	C3DHALL10_DATA_TYPE_32BIT_REG 0x0000

#define	C3DHALL10_DATA_TYPE_12BIT_XY_DATA 0x0040

#define	C3DHALL10_DATA_TYPE_12BIT_XZ_DATA 0x0080

#define	C3DHALL10_DATA_TYPE_12BIT_ZY_DATA 0x00C0

#define	C3DHALL10_DATA_TYPE_12BIT_XT_DATA 0x0100

#define	C3DHALL10_DATA_TYPE_12BIT_YT_DATA 0x0140

#define	C3DHALL10_DATA_TYPE_12BIT_ZT_DATA 0x0180

#define	C3DHALL10_DATA_TYPE_12BIT_AM_DATA 0x01C0

#define	C3DHALL10_DATA_TYPE_BIT_MASK 0x01C0

#define	C3DHALL10_DIAG_EN_DISABLE 0x0000

#define	C3DHALL10_DIAG_EN_ENABLE 0x0020

#define	C3DHALL10_DIAG_EN_BIT_MASK 0x0020

#define	C3DHALL10_Z_HLT_EN_DISABLE 0x0000

#define	C3DHALL10_Z_HLT_EN_ENABLE 0x0004

#define	C3DHALL10_Z_HLT_EN_BIT_MASK 0x0004

#define	C3DHALL10_Y_HLT_EN_DISABLE 0x0000

#define	C3DHALL10_Y_HLT_EN_ENABLE 0x0002

#define	C3DHALL10_Y_HLT_EN_BIT_MASK 0x0002

#define	C3DHALL10_X_HLT_EN_DISABLE 0x0000

#define	C3DHALL10_X_HLT_EN_ENABLE 0x0001

#define	C3DHALL10_X_HLT_EN_BIT_MASK 0x0001

#define	C3DHALL10_ALERT_LATCH_DISABLE 0x0000
	3D Hall 10 alert config register settings.

#define	C3DHALL10_ALERT_LATCH_ENABLE 0x2000

#define	C3DHALL10_ALERT_LATCH_BIT_MASK 0x2000

#define	C3DHALL10_ALERT_MODE_INTERRUPT 0x0000

#define	C3DHALL10_ALERT_MODE_SWITCH 0x1000

#define	C3DHALL10_ALERT_MODE_BIT_MASK 0x1000

#define	C3DHALL10_STATUS_ALRT_AFE_SYS_NO_ASSERT 0x0000

#define	C3DHALL10_STATUS_ALRT_AFE_SYS_ASSERT 0x0800

#define	C3DHALL10_STATUS_ALRT_BIT_MASK 0x0800

#define	C3DHALL10_RSLT_ALRT_NO_CONV_COMPLETE 0x0000

#define	C3DHALL10_RSLT_ALRT_CONV_COMPLETE 0x0100

#define	C3DHALL10_RSLT_ALRT_BIT_MASK 0x0100

#define	C3DHALL10_THRX_COUNT_1_CONV 0x0000

#define	C3DHALL10_THRX_COUNT_2_CONV 0x0010

#define	C3DHALL10_THRX_COUNT_3_CONV 0x0020

#define	C3DHALL10_THRX_COUNT_4_CONV 0x0030

#define	C3DHALL10_THRX_COUNT_BIT_MASK 0x0030

#define	C3DHALL10_T_THRX_ALRT_NO_CROSSED 0x0000

#define	C3DHALL10_T_THRX_ALRT_CROSSED 0x0008

#define	C3DHALL10_T_THRX_ALRT_BIT_MASK 0x0008

#define	C3DHALL10_Z_THRX_ALRT_NO_CROSSED 0x0000

#define	C3DHALL10_Z_THRX_ALRT_CROSSED 0x0004

#define	C3DHALL10_Z_THRX_ALRT_BIT_MASK 0x0004

#define	C3DHALL10_Y_THRX_ALRT_NO_CROSSED 0x0000

#define	C3DHALL10_Y_THRX_ALRT_CROSSED 0x0002

#define	C3DHALL10_Y_THRX_ALRT_BIT_MASK 0x0002

#define	C3DHALL10_X_THRX_ALRT_NO_CROSSED 0x0000

#define	C3DHALL10_X_THRX_ALRT_CROSSED 0x0001

#define	C3DHALL10_X_THRX_ALRT_BIT_MASK 0x0001

#define	C3DHALL10_GAIN_SELECTION_NO_AXIS 0x0000
	3D Hall 10 mag gain config register settings.

#define	C3DHALL10_GAIN_SELECTION_X_AXIS 0x4000

#define	C3DHALL10_GAIN_SELECTION_Y_AXIS 0x8000

#define	C3DHALL10_GAIN_SELECTION_Z_AXIS 0xC000

#define	C3DHALL10_GAIN_SELECTION_BIT_MASK 0xC000

#define	C3DHALL10_GAIN_VALUE_BIT_MASK 0x07FF

#define	C3DHALL10_CONV_STATUS_RDY 0x2000
	3D Hall 10 conv status register settings.

#define	C3DHALL10_CONV_STATUS_A 0x1000

#define	C3DHALL10_CONV_STATUS_T 0x0800

#define	C3DHALL10_CONV_STATUS_Z 0x0400

#define	C3DHALL10_CONV_STATUS_Y 0x0200

#define	C3DHALL10_CONV_STATUS_X 0x0100

#define	C3DHALL10_CONV_STATUS_SET_COUNT 0x0070

#define	C3DHALL10_CONV_STATUS_ALRT_STATUS 0x0003

#define	C3DHALL10_ANGLE_RESOLUTION 16.0
	3D Hall 10 calculation values.

#define	C3DHALL10_TEMP_SENS_T0 25.0

#define	C3DHALL10_TEMP_ADC_T0 17522

#define	C3DHALL10_TEMP_ADC_RESOLUTION 60.0

#define	C3DHALL10_XYZ_RESOLUTION 32768.0

#define	C3DHALL10_SPI_READ_MASK 0x80
	3D Hall 10 SPI read/write bit mask.

#define	C3DHALL10_SPI_WRITE_MASK 0x7F

#define	C3DHALL10_SET_DATA_SAMPLE_EDGE SET_SPI_DATA_SAMPLE_EDGE
	Data sample selection.

#define	C3DHALL10_SET_DATA_SAMPLE_MIDDLE SET_SPI_DATA_SAMPLE_MIDDLE

Detailed Description

Settings for registers of 3D Hall 10 Click driver.

Macro Definition Documentation

◆ C3DHALL10_ALERT_LATCH_BIT_MASK

#define C3DHALL10_ALERT_LATCH_BIT_MASK 0x2000

◆ C3DHALL10_ALERT_LATCH_DISABLE

#define C3DHALL10_ALERT_LATCH_DISABLE 0x0000

3D Hall 10 alert config register settings.

Specified settings for alert config register of 3D Hall 10 Click driver.

◆ C3DHALL10_ALERT_LATCH_ENABLE

#define C3DHALL10_ALERT_LATCH_ENABLE 0x2000

◆ C3DHALL10_ALERT_MODE_BIT_MASK

#define C3DHALL10_ALERT_MODE_BIT_MASK 0x1000

◆ C3DHALL10_ALERT_MODE_INTERRUPT

#define C3DHALL10_ALERT_MODE_INTERRUPT 0x0000

◆ C3DHALL10_ALERT_MODE_SWITCH

#define C3DHALL10_ALERT_MODE_SWITCH 0x1000

◆ C3DHALL10_ANGLE_EN_BIT_MASK

#define C3DHALL10_ANGLE_EN_BIT_MASK 0xC000

◆ C3DHALL10_ANGLE_EN_NO_ANGLE

#define C3DHALL10_ANGLE_EN_NO_ANGLE 0x0000

3D Hall 10 sensor config register settings.

Specified settings for sensor config register of 3D Hall 10 Click driver.

◆ C3DHALL10_ANGLE_EN_XY_ANGLE

#define C3DHALL10_ANGLE_EN_XY_ANGLE 0x4000

◆ C3DHALL10_ANGLE_EN_XZ_ANGLE

#define C3DHALL10_ANGLE_EN_XZ_ANGLE 0xC000

◆ C3DHALL10_ANGLE_EN_YZ_ANGLE

#define C3DHALL10_ANGLE_EN_YZ_ANGLE 0x8000

◆ C3DHALL10_ANGLE_RESOLUTION

#define C3DHALL10_ANGLE_RESOLUTION 16.0

3D Hall 10 calculation values.

Specified calculation values of 3D Hall 10 Click driver.

◆ C3DHALL10_CONV_AVG_16X

#define C3DHALL10_CONV_AVG_16X 0x4000

◆ C3DHALL10_CONV_AVG_1X

#define C3DHALL10_CONV_AVG_1X 0x0000

3D Hall 10 device config register settings.

Specified settings for device config register of 3D Hall 10 Click driver.

◆ C3DHALL10_CONV_AVG_2X

#define C3DHALL10_CONV_AVG_2X 0x1000

◆ C3DHALL10_CONV_AVG_32X

#define C3DHALL10_CONV_AVG_32X 0x5000

◆ C3DHALL10_CONV_AVG_4X

#define C3DHALL10_CONV_AVG_4X 0x2000

◆ C3DHALL10_CONV_AVG_8X

#define C3DHALL10_CONV_AVG_8X 0x3000

◆ C3DHALL10_CONV_AVG_BIT_MASK

#define C3DHALL10_CONV_AVG_BIT_MASK 0x7000

◆ C3DHALL10_CONV_STATUS_A

#define C3DHALL10_CONV_STATUS_A 0x1000

◆ C3DHALL10_CONV_STATUS_ALRT_STATUS

#define C3DHALL10_CONV_STATUS_ALRT_STATUS 0x0003

◆ C3DHALL10_CONV_STATUS_RDY

#define C3DHALL10_CONV_STATUS_RDY 0x2000

3D Hall 10 conv status register settings.

Specified settings for conv status register of 3D Hall 10 Click driver.

◆ C3DHALL10_CONV_STATUS_SET_COUNT

#define C3DHALL10_CONV_STATUS_SET_COUNT 0x0070

◆ C3DHALL10_CONV_STATUS_T

#define C3DHALL10_CONV_STATUS_T 0x0800

◆ C3DHALL10_CONV_STATUS_X

#define C3DHALL10_CONV_STATUS_X 0x0100

◆ C3DHALL10_CONV_STATUS_Y

#define C3DHALL10_CONV_STATUS_Y 0x0200

◆ C3DHALL10_CONV_STATUS_Z

#define C3DHALL10_CONV_STATUS_Z 0x0400

◆ C3DHALL10_DATA_TYPE_12BIT_AM_DATA

#define C3DHALL10_DATA_TYPE_12BIT_AM_DATA 0x01C0

◆ C3DHALL10_DATA_TYPE_12BIT_XT_DATA

#define C3DHALL10_DATA_TYPE_12BIT_XT_DATA 0x0100

◆ C3DHALL10_DATA_TYPE_12BIT_XY_DATA

#define C3DHALL10_DATA_TYPE_12BIT_XY_DATA 0x0040

◆ C3DHALL10_DATA_TYPE_12BIT_XZ_DATA

#define C3DHALL10_DATA_TYPE_12BIT_XZ_DATA 0x0080

◆ C3DHALL10_DATA_TYPE_12BIT_YT_DATA

#define C3DHALL10_DATA_TYPE_12BIT_YT_DATA 0x0140

◆ C3DHALL10_DATA_TYPE_12BIT_ZT_DATA

#define C3DHALL10_DATA_TYPE_12BIT_ZT_DATA 0x0180

◆ C3DHALL10_DATA_TYPE_12BIT_ZY_DATA

#define C3DHALL10_DATA_TYPE_12BIT_ZY_DATA 0x00C0

◆ C3DHALL10_DATA_TYPE_32BIT_REG

#define C3DHALL10_DATA_TYPE_32BIT_REG 0x0000

◆ C3DHALL10_DATA_TYPE_BIT_MASK

#define C3DHALL10_DATA_TYPE_BIT_MASK 0x01C0

◆ C3DHALL10_DIAG_EN_BIT_MASK

#define C3DHALL10_DIAG_EN_BIT_MASK 0x0020

◆ C3DHALL10_DIAG_EN_DISABLE

#define C3DHALL10_DIAG_EN_DISABLE 0x0000

◆ C3DHALL10_DIAG_EN_ENABLE

#define C3DHALL10_DIAG_EN_ENABLE 0x0020

◆ C3DHALL10_DIAG_SEL_ALL_DP_DIAG_ALL

#define C3DHALL10_DIAG_SEL_ALL_DP_DIAG_ALL 0x0000

3D Hall 10 system config register settings.

Specified settings for system config register of 3D Hall 10 Click driver.

◆ C3DHALL10_DIAG_SEL_ALL_DP_DIAG_SEQ

#define C3DHALL10_DIAG_SEL_ALL_DP_DIAG_SEQ 0x2000

◆ C3DHALL10_DIAG_SEL_BIT_MASK

#define C3DHALL10_DIAG_SEL_BIT_MASK 0x3000

◆ C3DHALL10_DIAG_SEL_EN_DP_ONLY_DIAG_ALL

#define C3DHALL10_DIAG_SEL_EN_DP_ONLY_DIAG_ALL 0x1000

◆ C3DHALL10_DIAG_SEL_EN_DP_ONLY_DIAG_SEQ

#define C3DHALL10_DIAG_SEL_EN_DP_ONLY_DIAG_SEQ 0x3000

◆ C3DHALL10_GAIN_SELECTION_BIT_MASK

#define C3DHALL10_GAIN_SELECTION_BIT_MASK 0xC000

◆ C3DHALL10_GAIN_SELECTION_NO_AXIS

#define C3DHALL10_GAIN_SELECTION_NO_AXIS 0x0000

3D Hall 10 mag gain config register settings.

Specified settings for mag gain config register of 3D Hall 10 Click driver.

◆ C3DHALL10_GAIN_SELECTION_X_AXIS

#define C3DHALL10_GAIN_SELECTION_X_AXIS 0x4000

◆ C3DHALL10_GAIN_SELECTION_Y_AXIS

#define C3DHALL10_GAIN_SELECTION_Y_AXIS 0x8000

◆ C3DHALL10_GAIN_SELECTION_Z_AXIS

#define C3DHALL10_GAIN_SELECTION_Z_AXIS 0xC000

◆ C3DHALL10_GAIN_VALUE_BIT_MASK

#define C3DHALL10_GAIN_VALUE_BIT_MASK 0x07FF

◆ C3DHALL10_MAG_CH_EN_BIT_MASK

#define C3DHALL10_MAG_CH_EN_BIT_MASK 0x03C0

◆ C3DHALL10_MAG_CH_EN_DISABLE

#define C3DHALL10_MAG_CH_EN_DISABLE 0x0000

◆ C3DHALL10_MAG_CH_EN_ENABLE_X

#define C3DHALL10_MAG_CH_EN_ENABLE_X 0x0040

◆ C3DHALL10_MAG_CH_EN_ENABLE_XY

#define C3DHALL10_MAG_CH_EN_ENABLE_XY 0x00C0

◆ C3DHALL10_MAG_CH_EN_ENABLE_XYX

#define C3DHALL10_MAG_CH_EN_ENABLE_XYX 0x0200

◆ C3DHALL10_MAG_CH_EN_ENABLE_XYZ

#define C3DHALL10_MAG_CH_EN_ENABLE_XYZ 0x01C0

◆ C3DHALL10_MAG_CH_EN_ENABLE_XYZYX

#define C3DHALL10_MAG_CH_EN_ENABLE_XYZYX 0x0380

◆ C3DHALL10_MAG_CH_EN_ENABLE_XYZZYX

#define C3DHALL10_MAG_CH_EN_ENABLE_XYZZYX 0x03C0

◆ C3DHALL10_MAG_CH_EN_ENABLE_XZX

#define C3DHALL10_MAG_CH_EN_ENABLE_XZX 0x0340

◆ C3DHALL10_MAG_CH_EN_ENABLE_Y

#define C3DHALL10_MAG_CH_EN_ENABLE_Y 0x0080

◆ C3DHALL10_MAG_CH_EN_ENABLE_YXY

#define C3DHALL10_MAG_CH_EN_ENABLE_YXY 0x0240

◆ C3DHALL10_MAG_CH_EN_ENABLE_YZ

#define C3DHALL10_MAG_CH_EN_ENABLE_YZ 0x0180

◆ C3DHALL10_MAG_CH_EN_ENABLE_YZY

#define C3DHALL10_MAG_CH_EN_ENABLE_YZY 0x0280

◆ C3DHALL10_MAG_CH_EN_ENABLE_Z

#define C3DHALL10_MAG_CH_EN_ENABLE_Z 0x0100

◆ C3DHALL10_MAG_CH_EN_ENABLE_ZX

#define C3DHALL10_MAG_CH_EN_ENABLE_ZX 0x0140

◆ C3DHALL10_MAG_CH_EN_ENABLE_ZXZ

#define C3DHALL10_MAG_CH_EN_ENABLE_ZXZ 0x0300

◆ C3DHALL10_MAG_CH_EN_ENABLE_ZYZ

#define C3DHALL10_MAG_CH_EN_ENABLE_ZYZ 0x02C0

◆ C3DHALL10_MAG_TEMPCO_0

#define C3DHALL10_MAG_TEMPCO_0 0x0000

◆ C3DHALL10_MAG_TEMPCO_0p03

#define C3DHALL10_MAG_TEMPCO_0p03 0x0200

◆ C3DHALL10_MAG_TEMPCO_0p12

#define C3DHALL10_MAG_TEMPCO_0p12 0x0100

◆ C3DHALL10_MAG_TEMPCO_0p2

#define C3DHALL10_MAG_TEMPCO_0p2 0x0300

◆ C3DHALL10_MAG_TEMPCO_BIT_MASK

#define C3DHALL10_MAG_TEMPCO_BIT_MASK 0x0300

◆ C3DHALL10_OPERATING_MODE_BIT_MASK

#define C3DHALL10_OPERATING_MODE_BIT_MASK 0x0070

◆ C3DHALL10_OPERATING_MODE_CONFIG

#define C3DHALL10_OPERATING_MODE_CONFIG 0x0000

◆ C3DHALL10_OPERATING_MODE_DEEP_SLEEP

#define C3DHALL10_OPERATING_MODE_DEEP_SLEEP 0x0060

◆ C3DHALL10_OPERATING_MODE_DUTY_CYCLED

#define C3DHALL10_OPERATING_MODE_DUTY_CYCLED 0x0040

◆ C3DHALL10_OPERATING_MODE_MEASURE

#define C3DHALL10_OPERATING_MODE_MEASURE 0x0020

◆ C3DHALL10_OPERATING_MODE_SLEEP

#define C3DHALL10_OPERATING_MODE_SLEEP 0x0050

◆ C3DHALL10_OPERATING_MODE_STANDBY

#define C3DHALL10_OPERATING_MODE_STANDBY 0x0010

◆ C3DHALL10_OPERATING_MODE_TRIGGER

#define C3DHALL10_OPERATING_MODE_TRIGGER 0x0030

◆ C3DHALL10_RSLT_ALRT_BIT_MASK

#define C3DHALL10_RSLT_ALRT_BIT_MASK 0x0100

◆ C3DHALL10_RSLT_ALRT_CONV_COMPLETE

#define C3DHALL10_RSLT_ALRT_CONV_COMPLETE 0x0100

◆ C3DHALL10_RSLT_ALRT_NO_CONV_COMPLETE

#define C3DHALL10_RSLT_ALRT_NO_CONV_COMPLETE 0x0000

◆ C3DHALL10_SET_DATA_SAMPLE_EDGE

#define C3DHALL10_SET_DATA_SAMPLE_EDGE SET_SPI_DATA_SAMPLE_EDGE

Data sample selection.

This macro sets data samples for SPI modules.

Note: Available only on Microchip PIC family devices. This macro will set data sampling for all SPI modules on MCU. Can be overwritten with c3dhall10_init which will set SET_SPI_DATA_SAMPLE_MIDDLE by default on the mapped mikrobus.

◆ C3DHALL10_SET_DATA_SAMPLE_MIDDLE

#define C3DHALL10_SET_DATA_SAMPLE_MIDDLE SET_SPI_DATA_SAMPLE_MIDDLE

◆ C3DHALL10_SLEEPTIME_1000MS

#define C3DHALL10_SLEEPTIME_1000MS 0x2400

◆ C3DHALL10_SLEEPTIME_100MS

#define C3DHALL10_SLEEPTIME_100MS 0x1C00

◆ C3DHALL10_SLEEPTIME_10MS

#define C3DHALL10_SLEEPTIME_10MS 0x0800

◆ C3DHALL10_SLEEPTIME_15MS

#define C3DHALL10_SLEEPTIME_15MS 0x0C00

◆ C3DHALL10_SLEEPTIME_1MS

#define C3DHALL10_SLEEPTIME_1MS 0x0000

◆ C3DHALL10_SLEEPTIME_20MS

#define C3DHALL10_SLEEPTIME_20MS 0x1000

◆ C3DHALL10_SLEEPTIME_30MS

#define C3DHALL10_SLEEPTIME_30MS 0x1400

◆ C3DHALL10_SLEEPTIME_500MS

#define C3DHALL10_SLEEPTIME_500MS 0x2000

◆ C3DHALL10_SLEEPTIME_50MS

#define C3DHALL10_SLEEPTIME_50MS 0x1800

◆ C3DHALL10_SLEEPTIME_5MS

#define C3DHALL10_SLEEPTIME_5MS 0x0400

◆ C3DHALL10_SLEEPTIME_BIT_MASK

#define C3DHALL10_SLEEPTIME_BIT_MASK 0x3C00

◆ C3DHALL10_SPI_READ_MASK

#define C3DHALL10_SPI_READ_MASK 0x80

3D Hall 10 SPI read/write bit mask.

Specified SPI read/write bit mask of 3D Hall 10 Click driver.

◆ C3DHALL10_SPI_WRITE_MASK

#define C3DHALL10_SPI_WRITE_MASK 0x7F

◆ C3DHALL10_STATUS_ALRT_AFE_SYS_ASSERT

#define C3DHALL10_STATUS_ALRT_AFE_SYS_ASSERT 0x0800

◆ C3DHALL10_STATUS_ALRT_AFE_SYS_NO_ASSERT

#define C3DHALL10_STATUS_ALRT_AFE_SYS_NO_ASSERT 0x0000

◆ C3DHALL10_STATUS_ALRT_BIT_MASK

#define C3DHALL10_STATUS_ALRT_BIT_MASK 0x0800

◆ C3DHALL10_T_CH_EN_BIT_MASK

#define C3DHALL10_T_CH_EN_BIT_MASK 0x0008

◆ C3DHALL10_T_CH_EN_DISABLE

#define C3DHALL10_T_CH_EN_DISABLE 0x0000

◆ C3DHALL10_T_CH_EN_ENABLE

#define C3DHALL10_T_CH_EN_ENABLE 0x0008

◆ C3DHALL10_T_HLT_EN_BIT_MASK

#define C3DHALL10_T_HLT_EN_BIT_MASK 0x0002

◆ C3DHALL10_T_HLT_EN_DISABLE

#define C3DHALL10_T_HLT_EN_DISABLE 0x0000

◆ C3DHALL10_T_HLT_EN_ENABLE

#define C3DHALL10_T_HLT_EN_ENABLE 0x0002

◆ C3DHALL10_T_RATE_BIT_MASK

#define C3DHALL10_T_RATE_BIT_MASK 0x0004

◆ C3DHALL10_T_RATE_ONCE_PER_CONV

#define C3DHALL10_T_RATE_ONCE_PER_CONV 0x0004

◆ C3DHALL10_T_RATE_PER_CONV_AVG

#define C3DHALL10_T_RATE_PER_CONV_AVG 0x0000

◆ C3DHALL10_T_THRX_ALRT_BIT_MASK

#define C3DHALL10_T_THRX_ALRT_BIT_MASK 0x0008

◆ C3DHALL10_T_THRX_ALRT_CROSSED

#define C3DHALL10_T_THRX_ALRT_CROSSED 0x0008

◆ C3DHALL10_T_THRX_ALRT_NO_CROSSED

#define C3DHALL10_T_THRX_ALRT_NO_CROSSED 0x0000

◆ C3DHALL10_TEMP_ADC_RESOLUTION

#define C3DHALL10_TEMP_ADC_RESOLUTION 60.0

◆ C3DHALL10_TEMP_ADC_T0

#define C3DHALL10_TEMP_ADC_T0 17522

◆ C3DHALL10_TEMP_SENS_T0

#define C3DHALL10_TEMP_SENS_T0 25.0

◆ C3DHALL10_THRX_COUNT_1_CONV

#define C3DHALL10_THRX_COUNT_1_CONV 0x0000

◆ C3DHALL10_THRX_COUNT_2_CONV

#define C3DHALL10_THRX_COUNT_2_CONV 0x0010

◆ C3DHALL10_THRX_COUNT_3_CONV

#define C3DHALL10_THRX_COUNT_3_CONV 0x0020

◆ C3DHALL10_THRX_COUNT_4_CONV

#define C3DHALL10_THRX_COUNT_4_CONV 0x0030

◆ C3DHALL10_THRX_COUNT_BIT_MASK

#define C3DHALL10_THRX_COUNT_BIT_MASK 0x0030

◆ C3DHALL10_TRIGGER_MODE_ALERT_PULSE

#define C3DHALL10_TRIGGER_MODE_ALERT_PULSE 0x0400

◆ C3DHALL10_TRIGGER_MODE_BIT_MASK

#define C3DHALL10_TRIGGER_MODE_BIT_MASK 0x0600

◆ C3DHALL10_TRIGGER_MODE_CS_PULSE

#define C3DHALL10_TRIGGER_MODE_CS_PULSE 0x0200

◆ C3DHALL10_TRIGGER_MODE_SPI_CMD

#define C3DHALL10_TRIGGER_MODE_SPI_CMD 0x0000

◆ C3DHALL10_X_HLT_EN_BIT_MASK

#define C3DHALL10_X_HLT_EN_BIT_MASK 0x0001

◆ C3DHALL10_X_HLT_EN_DISABLE

#define C3DHALL10_X_HLT_EN_DISABLE 0x0000

◆ C3DHALL10_X_HLT_EN_ENABLE

#define C3DHALL10_X_HLT_EN_ENABLE 0x0001

◆ C3DHALL10_X_RANGE_100mT

#define C3DHALL10_X_RANGE_100mT 0x0002

◆ C3DHALL10_X_RANGE_25mT

#define C3DHALL10_X_RANGE_25mT 0x0001

◆ C3DHALL10_X_RANGE_50mT

#define C3DHALL10_X_RANGE_50mT 0x0000

◆ C3DHALL10_X_RANGE_BIT_MASK

#define C3DHALL10_X_RANGE_BIT_MASK 0x0003

◆ C3DHALL10_X_THRX_ALRT_BIT_MASK

#define C3DHALL10_X_THRX_ALRT_BIT_MASK 0x0001

◆ C3DHALL10_X_THRX_ALRT_CROSSED

#define C3DHALL10_X_THRX_ALRT_CROSSED 0x0001

◆ C3DHALL10_X_THRX_ALRT_NO_CROSSED

#define C3DHALL10_X_THRX_ALRT_NO_CROSSED 0x0000

◆ C3DHALL10_XYZ_RESOLUTION

#define C3DHALL10_XYZ_RESOLUTION 32768.0

◆ C3DHALL10_Y_HLT_EN_BIT_MASK

#define C3DHALL10_Y_HLT_EN_BIT_MASK 0x0002

◆ C3DHALL10_Y_HLT_EN_DISABLE

#define C3DHALL10_Y_HLT_EN_DISABLE 0x0000

◆ C3DHALL10_Y_HLT_EN_ENABLE

#define C3DHALL10_Y_HLT_EN_ENABLE 0x0002

◆ C3DHALL10_Y_RANGE_100mT

#define C3DHALL10_Y_RANGE_100mT 0x0008

◆ C3DHALL10_Y_RANGE_25mT

#define C3DHALL10_Y_RANGE_25mT 0x0004

◆ C3DHALL10_Y_RANGE_50mT

#define C3DHALL10_Y_RANGE_50mT 0x0000

◆ C3DHALL10_Y_RANGE_BIT_MASK

#define C3DHALL10_Y_RANGE_BIT_MASK 0x000C

◆ C3DHALL10_Y_THRX_ALRT_BIT_MASK

#define C3DHALL10_Y_THRX_ALRT_BIT_MASK 0x0002

◆ C3DHALL10_Y_THRX_ALRT_CROSSED

#define C3DHALL10_Y_THRX_ALRT_CROSSED 0x0002

◆ C3DHALL10_Y_THRX_ALRT_NO_CROSSED

#define C3DHALL10_Y_THRX_ALRT_NO_CROSSED 0x0000

◆ C3DHALL10_Z_HLT_EN_BIT_MASK

#define C3DHALL10_Z_HLT_EN_BIT_MASK 0x0004

◆ C3DHALL10_Z_HLT_EN_DISABLE

#define C3DHALL10_Z_HLT_EN_DISABLE 0x0000

◆ C3DHALL10_Z_HLT_EN_ENABLE

#define C3DHALL10_Z_HLT_EN_ENABLE 0x0004

◆ C3DHALL10_Z_RANGE_100mT

#define C3DHALL10_Z_RANGE_100mT 0x0020

◆ C3DHALL10_Z_RANGE_25mT

#define C3DHALL10_Z_RANGE_25mT 0x0010

◆ C3DHALL10_Z_RANGE_50mT

#define C3DHALL10_Z_RANGE_50mT 0x0000

◆ C3DHALL10_Z_RANGE_BIT_MASK

#define C3DHALL10_Z_RANGE_BIT_MASK 0x0030

◆ C3DHALL10_Z_THRX_ALRT_BIT_MASK

#define C3DHALL10_Z_THRX_ALRT_BIT_MASK 0x0004

◆ C3DHALL10_Z_THRX_ALRT_CROSSED

#define C3DHALL10_Z_THRX_ALRT_CROSSED 0x0004

◆ C3DHALL10_Z_THRX_ALRT_NO_CROSSED

#define C3DHALL10_Z_THRX_ALRT_NO_CROSSED 0x0000

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