Here is a list of all macros with links to the files they belong to:

- c -

• C3DHALL10_ALERT_LATCH_BIT_MASK : c3dhall10.h
• C3DHALL10_ALERT_LATCH_DISABLE : c3dhall10.h
• C3DHALL10_ALERT_LATCH_ENABLE : c3dhall10.h
• C3DHALL10_ALERT_MODE_BIT_MASK : c3dhall10.h
• C3DHALL10_ALERT_MODE_INTERRUPT : c3dhall10.h
• C3DHALL10_ALERT_MODE_SWITCH : c3dhall10.h
• C3DHALL10_ANGLE_EN_BIT_MASK : c3dhall10.h
• C3DHALL10_ANGLE_EN_NO_ANGLE : c3dhall10.h
• C3DHALL10_ANGLE_EN_XY_ANGLE : c3dhall10.h
• C3DHALL10_ANGLE_EN_XZ_ANGLE : c3dhall10.h
• C3DHALL10_ANGLE_EN_YZ_ANGLE : c3dhall10.h
• C3DHALL10_ANGLE_RESOLUTION : c3dhall10.h
• C3DHALL10_CONV_AVG_16X : c3dhall10.h
• C3DHALL10_CONV_AVG_1X : c3dhall10.h
• C3DHALL10_CONV_AVG_2X : c3dhall10.h
• C3DHALL10_CONV_AVG_32X : c3dhall10.h
• C3DHALL10_CONV_AVG_4X : c3dhall10.h
• C3DHALL10_CONV_AVG_8X : c3dhall10.h
• C3DHALL10_CONV_AVG_BIT_MASK : c3dhall10.h
• C3DHALL10_CONV_STATUS_A : c3dhall10.h
• C3DHALL10_CONV_STATUS_ALRT_STATUS : c3dhall10.h
• C3DHALL10_CONV_STATUS_RDY : c3dhall10.h
• C3DHALL10_CONV_STATUS_SET_COUNT : c3dhall10.h
• C3DHALL10_CONV_STATUS_T : c3dhall10.h
• C3DHALL10_CONV_STATUS_X : c3dhall10.h
• C3DHALL10_CONV_STATUS_Y : c3dhall10.h
• C3DHALL10_CONV_STATUS_Z : c3dhall10.h
• C3DHALL10_DATA_TYPE_12BIT_AM_DATA : c3dhall10.h
• C3DHALL10_DATA_TYPE_12BIT_XT_DATA : c3dhall10.h
• C3DHALL10_DATA_TYPE_12BIT_XY_DATA : c3dhall10.h
• C3DHALL10_DATA_TYPE_12BIT_XZ_DATA : c3dhall10.h
• C3DHALL10_DATA_TYPE_12BIT_YT_DATA : c3dhall10.h
• C3DHALL10_DATA_TYPE_12BIT_ZT_DATA : c3dhall10.h
• C3DHALL10_DATA_TYPE_12BIT_ZY_DATA : c3dhall10.h
• C3DHALL10_DATA_TYPE_32BIT_REG : c3dhall10.h
• C3DHALL10_DATA_TYPE_BIT_MASK : c3dhall10.h
• C3DHALL10_DIAG_EN_BIT_MASK : c3dhall10.h
• C3DHALL10_DIAG_EN_DISABLE : c3dhall10.h
• C3DHALL10_DIAG_EN_ENABLE : c3dhall10.h
• C3DHALL10_DIAG_SEL_ALL_DP_DIAG_ALL : c3dhall10.h
• C3DHALL10_DIAG_SEL_ALL_DP_DIAG_SEQ : c3dhall10.h
• C3DHALL10_DIAG_SEL_BIT_MASK : c3dhall10.h
• C3DHALL10_DIAG_SEL_EN_DP_ONLY_DIAG_ALL : c3dhall10.h
• C3DHALL10_DIAG_SEL_EN_DP_ONLY_DIAG_SEQ : c3dhall10.h
• C3DHALL10_GAIN_SELECTION_BIT_MASK : c3dhall10.h
• C3DHALL10_GAIN_SELECTION_NO_AXIS : c3dhall10.h
• C3DHALL10_GAIN_SELECTION_X_AXIS : c3dhall10.h
• C3DHALL10_GAIN_SELECTION_Y_AXIS : c3dhall10.h
• C3DHALL10_GAIN_SELECTION_Z_AXIS : c3dhall10.h
• C3DHALL10_GAIN_VALUE_BIT_MASK : c3dhall10.h
• C3DHALL10_MAG_CH_EN_BIT_MASK : c3dhall10.h
• C3DHALL10_MAG_CH_EN_DISABLE : c3dhall10.h
• C3DHALL10_MAG_CH_EN_ENABLE_X : c3dhall10.h
• C3DHALL10_MAG_CH_EN_ENABLE_XY : c3dhall10.h
• C3DHALL10_MAG_CH_EN_ENABLE_XYX : c3dhall10.h
• C3DHALL10_MAG_CH_EN_ENABLE_XYZ : c3dhall10.h
• C3DHALL10_MAG_CH_EN_ENABLE_XYZYX : c3dhall10.h
• C3DHALL10_MAG_CH_EN_ENABLE_XYZZYX : c3dhall10.h
• C3DHALL10_MAG_CH_EN_ENABLE_XZX : c3dhall10.h
• C3DHALL10_MAG_CH_EN_ENABLE_Y : c3dhall10.h
• C3DHALL10_MAG_CH_EN_ENABLE_YXY : c3dhall10.h
• C3DHALL10_MAG_CH_EN_ENABLE_YZ : c3dhall10.h
• C3DHALL10_MAG_CH_EN_ENABLE_YZY : c3dhall10.h
• C3DHALL10_MAG_CH_EN_ENABLE_Z : c3dhall10.h
• C3DHALL10_MAG_CH_EN_ENABLE_ZX : c3dhall10.h
• C3DHALL10_MAG_CH_EN_ENABLE_ZXZ : c3dhall10.h
• C3DHALL10_MAG_CH_EN_ENABLE_ZYZ : c3dhall10.h
• C3DHALL10_MAG_TEMPCO_0 : c3dhall10.h
• C3DHALL10_MAG_TEMPCO_0p03 : c3dhall10.h
• C3DHALL10_MAG_TEMPCO_0p12 : c3dhall10.h
• C3DHALL10_MAG_TEMPCO_0p2 : c3dhall10.h
• C3DHALL10_MAG_TEMPCO_BIT_MASK : c3dhall10.h
• C3DHALL10_MAP_MIKROBUS : c3dhall10.h
• C3DHALL10_OPERATING_MODE_BIT_MASK : c3dhall10.h
• C3DHALL10_OPERATING_MODE_CONFIG : c3dhall10.h
• C3DHALL10_OPERATING_MODE_DEEP_SLEEP : c3dhall10.h
• C3DHALL10_OPERATING_MODE_DUTY_CYCLED : c3dhall10.h
• C3DHALL10_OPERATING_MODE_MEASURE : c3dhall10.h
• C3DHALL10_OPERATING_MODE_SLEEP : c3dhall10.h
• C3DHALL10_OPERATING_MODE_STANDBY : c3dhall10.h
• C3DHALL10_OPERATING_MODE_TRIGGER : c3dhall10.h
• C3DHALL10_REG_AFE_STATUS : c3dhall10.h
• C3DHALL10_REG_ALERT_CONFIG : c3dhall10.h
• C3DHALL10_REG_ANGLE_RESULT : c3dhall10.h
• C3DHALL10_REG_CONV_STATUS : c3dhall10.h
• C3DHALL10_REG_DEVICE_CONFIG : c3dhall10.h
• C3DHALL10_REG_MAG_GAIN_CONFIG : c3dhall10.h
• C3DHALL10_REG_MAG_OFFSET_CONFIG : c3dhall10.h
• C3DHALL10_REG_MAGNITUDE_RESULT : c3dhall10.h
• C3DHALL10_REG_OSC_MONITOR : c3dhall10.h
• C3DHALL10_REG_SENSOR_CONFIG : c3dhall10.h
• C3DHALL10_REG_SYS_STATUS : c3dhall10.h
• C3DHALL10_REG_SYSTEM_CONFIG : c3dhall10.h
• C3DHALL10_REG_T_THRX_CONFIG : c3dhall10.h
• C3DHALL10_REG_TEMP_RESULT : c3dhall10.h
• C3DHALL10_REG_TEST_CONFIG : c3dhall10.h
• C3DHALL10_REG_X_CH_RESULT : c3dhall10.h
• C3DHALL10_REG_X_THRX_CONFIG : c3dhall10.h
• C3DHALL10_REG_Y_CH_RESULT : c3dhall10.h
• C3DHALL10_REG_Y_THRX_CONFIG : c3dhall10.h
• C3DHALL10_REG_Z_CH_RESULT : c3dhall10.h
• C3DHALL10_REG_Z_THRX_CONFIG : c3dhall10.h
• C3DHALL10_RSLT_ALRT_BIT_MASK : c3dhall10.h
• C3DHALL10_RSLT_ALRT_CONV_COMPLETE : c3dhall10.h
• C3DHALL10_RSLT_ALRT_NO_CONV_COMPLETE : c3dhall10.h
• C3DHALL10_SET_DATA_SAMPLE_EDGE : c3dhall10.h
• C3DHALL10_SET_DATA_SAMPLE_MIDDLE : c3dhall10.h
• C3DHALL10_SLEEPTIME_1000MS : c3dhall10.h
• C3DHALL10_SLEEPTIME_100MS : c3dhall10.h
• C3DHALL10_SLEEPTIME_10MS : c3dhall10.h
• C3DHALL10_SLEEPTIME_15MS : c3dhall10.h
• C3DHALL10_SLEEPTIME_1MS : c3dhall10.h
• C3DHALL10_SLEEPTIME_20MS : c3dhall10.h
• C3DHALL10_SLEEPTIME_30MS : c3dhall10.h
• C3DHALL10_SLEEPTIME_500MS : c3dhall10.h
• C3DHALL10_SLEEPTIME_50MS : c3dhall10.h
• C3DHALL10_SLEEPTIME_5MS : c3dhall10.h
• C3DHALL10_SLEEPTIME_BIT_MASK : c3dhall10.h
• C3DHALL10_SPI_READ_MASK : c3dhall10.h
• C3DHALL10_SPI_WRITE_MASK : c3dhall10.h
• C3DHALL10_STATUS_ALRT_AFE_SYS_ASSERT : c3dhall10.h
• C3DHALL10_STATUS_ALRT_AFE_SYS_NO_ASSERT : c3dhall10.h
• C3DHALL10_STATUS_ALRT_BIT_MASK : c3dhall10.h
• C3DHALL10_T_CH_EN_BIT_MASK : c3dhall10.h
• C3DHALL10_T_CH_EN_DISABLE : c3dhall10.h
• C3DHALL10_T_CH_EN_ENABLE : c3dhall10.h
• C3DHALL10_T_HLT_EN_BIT_MASK : c3dhall10.h
• C3DHALL10_T_HLT_EN_DISABLE : c3dhall10.h
• C3DHALL10_T_HLT_EN_ENABLE : c3dhall10.h
• C3DHALL10_T_RATE_BIT_MASK : c3dhall10.h
• C3DHALL10_T_RATE_ONCE_PER_CONV : c3dhall10.h
• C3DHALL10_T_RATE_PER_CONV_AVG : c3dhall10.h
• C3DHALL10_T_THRX_ALRT_BIT_MASK : c3dhall10.h
• C3DHALL10_T_THRX_ALRT_CROSSED : c3dhall10.h
• C3DHALL10_T_THRX_ALRT_NO_CROSSED : c3dhall10.h
• C3DHALL10_TEMP_ADC_RESOLUTION : c3dhall10.h
• C3DHALL10_TEMP_ADC_T0 : c3dhall10.h
• C3DHALL10_TEMP_SENS_T0 : c3dhall10.h
• C3DHALL10_THRX_COUNT_1_CONV : c3dhall10.h
• C3DHALL10_THRX_COUNT_2_CONV : c3dhall10.h
• C3DHALL10_THRX_COUNT_3_CONV : c3dhall10.h
• C3DHALL10_THRX_COUNT_4_CONV : c3dhall10.h
• C3DHALL10_THRX_COUNT_BIT_MASK : c3dhall10.h
• C3DHALL10_TRIGGER_MODE_ALERT_PULSE : c3dhall10.h
• C3DHALL10_TRIGGER_MODE_BIT_MASK : c3dhall10.h
• C3DHALL10_TRIGGER_MODE_CS_PULSE : c3dhall10.h
• C3DHALL10_TRIGGER_MODE_SPI_CMD : c3dhall10.h
• C3DHALL10_X_HLT_EN_BIT_MASK : c3dhall10.h
• C3DHALL10_X_HLT_EN_DISABLE : c3dhall10.h
• C3DHALL10_X_HLT_EN_ENABLE : c3dhall10.h
• C3DHALL10_X_RANGE_100mT : c3dhall10.h
• C3DHALL10_X_RANGE_25mT : c3dhall10.h
• C3DHALL10_X_RANGE_50mT : c3dhall10.h
• C3DHALL10_X_RANGE_BIT_MASK : c3dhall10.h
• C3DHALL10_X_THRX_ALRT_BIT_MASK : c3dhall10.h
• C3DHALL10_X_THRX_ALRT_CROSSED : c3dhall10.h
• C3DHALL10_X_THRX_ALRT_NO_CROSSED : c3dhall10.h
• C3DHALL10_XYZ_RESOLUTION : c3dhall10.h
• C3DHALL10_Y_HLT_EN_BIT_MASK : c3dhall10.h
• C3DHALL10_Y_HLT_EN_DISABLE : c3dhall10.h
• C3DHALL10_Y_HLT_EN_ENABLE : c3dhall10.h
• C3DHALL10_Y_RANGE_100mT : c3dhall10.h
• C3DHALL10_Y_RANGE_25mT : c3dhall10.h
• C3DHALL10_Y_RANGE_50mT : c3dhall10.h
• C3DHALL10_Y_RANGE_BIT_MASK : c3dhall10.h
• C3DHALL10_Y_THRX_ALRT_BIT_MASK : c3dhall10.h
• C3DHALL10_Y_THRX_ALRT_CROSSED : c3dhall10.h
• C3DHALL10_Y_THRX_ALRT_NO_CROSSED : c3dhall10.h
• C3DHALL10_Z_HLT_EN_BIT_MASK : c3dhall10.h
• C3DHALL10_Z_HLT_EN_DISABLE : c3dhall10.h
• C3DHALL10_Z_HLT_EN_ENABLE : c3dhall10.h
• C3DHALL10_Z_RANGE_100mT : c3dhall10.h
• C3DHALL10_Z_RANGE_25mT : c3dhall10.h
• C3DHALL10_Z_RANGE_50mT : c3dhall10.h
• C3DHALL10_Z_RANGE_BIT_MASK : c3dhall10.h
• C3DHALL10_Z_THRX_ALRT_BIT_MASK : c3dhall10.h
• C3DHALL10_Z_THRX_ALRT_CROSSED : c3dhall10.h
• C3DHALL10_Z_THRX_ALRT_NO_CROSSED : c3dhall10.h

- s -

• SET_SPI_DATA_SAMPLE_EDGE : spi_specifics.h
• SET_SPI_DATA_SAMPLE_MIDDLE : spi_specifics.h