c3dhall5 2.0.0.0
Config register A

Macros

#define C3DHALL5_CFG_A_COMP_TEMP_ENABLE   0x80
 
#define C3DHALL5_CFG_A_COMP_TEMP_DISABLE   0x00
 
#define C3DHALL5_CFG_A_REBOOT_MEM_CONTENT   0x40
 
#define C3DHALL5_CFG_A_NORMAL_MODE   0x00
 
#define C3DHALL5_CFG_A_SOFTRESET   0x20
 
#define C3DHALL5_CFG_A_HIGH_RESOLUTION_MODE   0x00
 
#define C3DHALL5_CFG_A_LOW_POWER_MODE   0x10
 
#define C3DHALL5_CFG_A_ODR_10Hz   0x00
 
#define C3DHALL5_CFG_A_ODR_20Hz   0x04
 
#define C3DHALL5_CFG_A_ODR_50Hz   0x08
 
#define C3DHALL5_CFG_A_ODR_100Hz   0x0C
 
#define C3DHALL5_CFG_A_MODE_CONTINUOUS   0x00
 
#define C3DHALL5_CFG_A_MODE_SINGLE   0x01
 
#define C3DHALL5_CFG_A_MODE_IDLE   0x02
 

Detailed Description

Macro Definition Documentation

◆ C3DHALL5_CFG_A_COMP_TEMP_DISABLE

#define C3DHALL5_CFG_A_COMP_TEMP_DISABLE   0x00

◆ C3DHALL5_CFG_A_COMP_TEMP_ENABLE

#define C3DHALL5_CFG_A_COMP_TEMP_ENABLE   0x80

◆ C3DHALL5_CFG_A_HIGH_RESOLUTION_MODE

#define C3DHALL5_CFG_A_HIGH_RESOLUTION_MODE   0x00

◆ C3DHALL5_CFG_A_LOW_POWER_MODE

#define C3DHALL5_CFG_A_LOW_POWER_MODE   0x10

◆ C3DHALL5_CFG_A_MODE_CONTINUOUS

#define C3DHALL5_CFG_A_MODE_CONTINUOUS   0x00

◆ C3DHALL5_CFG_A_MODE_IDLE

#define C3DHALL5_CFG_A_MODE_IDLE   0x02

◆ C3DHALL5_CFG_A_MODE_SINGLE

#define C3DHALL5_CFG_A_MODE_SINGLE   0x01

◆ C3DHALL5_CFG_A_NORMAL_MODE

#define C3DHALL5_CFG_A_NORMAL_MODE   0x00

◆ C3DHALL5_CFG_A_ODR_100Hz

#define C3DHALL5_CFG_A_ODR_100Hz   0x0C

◆ C3DHALL5_CFG_A_ODR_10Hz

#define C3DHALL5_CFG_A_ODR_10Hz   0x00

◆ C3DHALL5_CFG_A_ODR_20Hz

#define C3DHALL5_CFG_A_ODR_20Hz   0x04

◆ C3DHALL5_CFG_A_ODR_50Hz

#define C3DHALL5_CFG_A_ODR_50Hz   0x08

◆ C3DHALL5_CFG_A_REBOOT_MEM_CONTENT

#define C3DHALL5_CFG_A_REBOOT_MEM_CONTENT   0x40

◆ C3DHALL5_CFG_A_SOFTRESET

#define C3DHALL5_CFG_A_SOFTRESET   0x20