c3dhall5 2.0.0.0
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Macros | |
#define | C3DHALL5_CFG_A_COMP_TEMP_ENABLE 0x80 |
#define | C3DHALL5_CFG_A_COMP_TEMP_DISABLE 0x00 |
#define | C3DHALL5_CFG_A_REBOOT_MEM_CONTENT 0x40 |
#define | C3DHALL5_CFG_A_NORMAL_MODE 0x00 |
#define | C3DHALL5_CFG_A_SOFTRESET 0x20 |
#define | C3DHALL5_CFG_A_HIGH_RESOLUTION_MODE 0x00 |
#define | C3DHALL5_CFG_A_LOW_POWER_MODE 0x10 |
#define | C3DHALL5_CFG_A_ODR_10Hz 0x00 |
#define | C3DHALL5_CFG_A_ODR_20Hz 0x04 |
#define | C3DHALL5_CFG_A_ODR_50Hz 0x08 |
#define | C3DHALL5_CFG_A_ODR_100Hz 0x0C |
#define | C3DHALL5_CFG_A_MODE_CONTINUOUS 0x00 |
#define | C3DHALL5_CFG_A_MODE_SINGLE 0x01 |
#define | C3DHALL5_CFG_A_MODE_IDLE 0x02 |
#define C3DHALL5_CFG_A_COMP_TEMP_DISABLE 0x00 |
#define C3DHALL5_CFG_A_COMP_TEMP_ENABLE 0x80 |
#define C3DHALL5_CFG_A_HIGH_RESOLUTION_MODE 0x00 |
#define C3DHALL5_CFG_A_LOW_POWER_MODE 0x10 |
#define C3DHALL5_CFG_A_MODE_CONTINUOUS 0x00 |
#define C3DHALL5_CFG_A_MODE_IDLE 0x02 |
#define C3DHALL5_CFG_A_MODE_SINGLE 0x01 |
#define C3DHALL5_CFG_A_NORMAL_MODE 0x00 |
#define C3DHALL5_CFG_A_ODR_100Hz 0x0C |
#define C3DHALL5_CFG_A_ODR_10Hz 0x00 |
#define C3DHALL5_CFG_A_ODR_20Hz 0x04 |
#define C3DHALL5_CFG_A_ODR_50Hz 0x08 |
#define C3DHALL5_CFG_A_REBOOT_MEM_CONTENT 0x40 |
#define C3DHALL5_CFG_A_SOFTRESET 0x20 |