Here is a list of all macros with links to the files they belong to:

- c -

• C3DHALL5_AXIS_X : c3dhall5.h
• C3DHALL5_AXIS_Y : c3dhall5.h
• C3DHALL5_AXIS_Z : c3dhall5.h
• C3DHALL5_CFG_A_COMP_TEMP_DISABLE : c3dhall5.h
• C3DHALL5_CFG_A_COMP_TEMP_ENABLE : c3dhall5.h
• C3DHALL5_CFG_A_HIGH_RESOLUTION_MODE : c3dhall5.h
• C3DHALL5_CFG_A_LOW_POWER_MODE : c3dhall5.h
• C3DHALL5_CFG_A_MODE_CONTINUOUS : c3dhall5.h
• C3DHALL5_CFG_A_MODE_IDLE : c3dhall5.h
• C3DHALL5_CFG_A_MODE_SINGLE : c3dhall5.h
• C3DHALL5_CFG_A_NORMAL_MODE : c3dhall5.h
• C3DHALL5_CFG_A_ODR_100Hz : c3dhall5.h
• C3DHALL5_CFG_A_ODR_10Hz : c3dhall5.h
• C3DHALL5_CFG_A_ODR_20Hz : c3dhall5.h
• C3DHALL5_CFG_A_ODR_50Hz : c3dhall5.h
• C3DHALL5_CFG_A_REBOOT_MEM_CONTENT : c3dhall5.h
• C3DHALL5_CFG_A_SOFTRESET : c3dhall5.h
• C3DHALL5_CFG_B_INT_ON_DATA_OFF : c3dhall5.h
• C3DHALL5_CFG_B_LPF_DISABLE_ODR_2 : c3dhall5.h
• C3DHALL5_CFG_B_LPF_ENABLE_ODR_4 : c3dhall5.h
• C3DHALL5_CFG_B_OFFSET_DISABLE : c3dhall5.h
• C3DHALL5_CFG_B_OFFSET_ENABLE : c3dhall5.h
• C3DHALL5_CFG_B_OFFSET_IN_SINGLE_MODE_DISABLE : c3dhall5.h
• C3DHALL5_CFG_B_OFFSET_IN_SINGLE_MODE_ENABLE : c3dhall5.h
• C3DHALL5_CFG_B_SET_PULSE_63_ODR : c3dhall5.h
• C3DHALL5_CFG_B_SET_PULSE_PD_CONDITION : c3dhall5.h
• C3DHALL5_CFG_C_BLE_ENABLE : c3dhall5.h
• C3DHALL5_CFG_C_DRDY_ON_PIN : c3dhall5.h
• C3DHALL5_CFG_C_I2C_DISABLE : c3dhall5.h
• C3DHALL5_CFG_C_INT_ON_PIN : c3dhall5.h
• C3DHALL5_CFG_C_INT_ON_PIN_DISABLE : c3dhall5.h
• C3DHALL5_CFG_C_SELF_TEST : c3dhall5.h
• C3DHALL5_I_AM : c3dhall5.h
• C3DHALL5_INIT_ERROR : c3dhall5.h
• C3DHALL5_INT_CTRL_IEA_0_SIGNALS_AN_INT : c3dhall5.h
• C3DHALL5_INT_CTRL_IEA_1_SIGNALS_AN_INT : c3dhall5.h
• C3DHALL5_INT_CTRL_IEL_INT_IS_LATCHED : c3dhall5.h
• C3DHALL5_INT_CTRL_IEL_INT_IS_PILSED : c3dhall5.h
• C3DHALL5_INT_CTRL_IEN_INT_DISABLE : c3dhall5.h
• C3DHALL5_INT_CTRL_IEN_INT_ENABLE : c3dhall5.h
• C3DHALL5_INT_CTRL_X_AXIS_ENABLE : c3dhall5.h
• C3DHALL5_INT_CTRL_Y_AXIS_ENABLE : c3dhall5.h
• C3DHALL5_INT_CTRL_Z_AXIS_ENABLE : c3dhall5.h
• C3DHALL5_INT_SOURCE_NEG_TH_N : c3dhall5.h
• C3DHALL5_INT_SOURCE_NEG_TH_X : c3dhall5.h
• C3DHALL5_INT_SOURCE_NEG_TH_Y : c3dhall5.h
• C3DHALL5_INT_SOURCE_POS_TH_X : c3dhall5.h
• C3DHALL5_INT_SOURCE_POS_TH_Y : c3dhall5.h
• C3DHALL5_INT_SOURCE_POS_TH_Z : c3dhall5.h
• C3DHALL5_MAP_MIKROBUS : c3dhall5.h
• C3DHALL5_MASTER_I2C : c3dhall5.h
• C3DHALL5_MASTER_SPI : c3dhall5.h
• C3DHALL5_OFFSET_AXIS_X : c3dhall5.h
• C3DHALL5_OFFSET_AXIS_Y : c3dhall5.h
• C3DHALL5_OFFSET_AXIS_Z : c3dhall5.h
• C3DHALL5_OK : c3dhall5.h
• C3DHALL5_REG_CONFIG_A : c3dhall5.h
• C3DHALL5_REG_CONFIG_B : c3dhall5.h
• C3DHALL5_REG_CONFIG_C : c3dhall5.h
• C3DHALL5_REG_INT_CTRL : c3dhall5.h
• C3DHALL5_REG_INT_SOURCE : c3dhall5.h
• C3DHALL5_REG_INT_THS_LSB : c3dhall5.h
• C3DHALL5_REG_INT_THS_MSB : c3dhall5.h
• C3DHALL5_REG_OFFSET_X_LSB : c3dhall5.h
• C3DHALL5_REG_OFFSET_X_MSB : c3dhall5.h
• C3DHALL5_REG_OFFSET_Y_LSB : c3dhall5.h
• C3DHALL5_REG_OFFSET_Y_MSB : c3dhall5.h
• C3DHALL5_REG_OFFSET_Z_LSB : c3dhall5.h
• C3DHALL5_REG_OFFSET_Z_MSB : c3dhall5.h
• C3DHALL5_REG_STATUS : c3dhall5.h
• C3DHALL5_REG_TEMP_LSB : c3dhall5.h
• C3DHALL5_REG_TEMP_MSB : c3dhall5.h
• C3DHALL5_REG_WHO_AM_I : c3dhall5.h
• C3DHALL5_REG_X_AXIS_LSB : c3dhall5.h
• C3DHALL5_REG_X_AXIS_MSB : c3dhall5.h
• C3DHALL5_REG_Y_AXIS_LSB : c3dhall5.h
• C3DHALL5_REG_Y_AXIS_MSB : c3dhall5.h
• C3DHALL5_REG_Z_AXIS_LSB : c3dhall5.h
• C3DHALL5_REG_Z_AXIS_MSB : c3dhall5.h
• C3DHALL5_RETVAL : c3dhall5.h
• C3DHALL5_STATUS_X_DATA_OVERRUN : c3dhall5.h
• C3DHALL5_STATUS_X_NEW_DATA : c3dhall5.h
• C3DHALL5_STATUS_XYZ_DATA_OVERRUN : c3dhall5.h
• C3DHALL5_STATUS_XYZ_NEW_DATA : c3dhall5.h
• C3DHALL5_STATUS_Y_DATA_OVERRUN : c3dhall5.h
• C3DHALL5_STATUS_Y_NEW_DATA : c3dhall5.h
• C3DHALL5_STATUS_Z_DATA_OVERRUN : c3dhall5.h
• C3DHALL5_STATUS_Z_NEW_DATA : c3dhall5.h