c3dhall5 2.0.0.0
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Macros | |
#define | C3DHALL5_CFG_B_OFFSET_IN_SINGLE_MODE_ENABLE 0x10 |
#define | C3DHALL5_CFG_B_OFFSET_IN_SINGLE_MODE_DISABLE 0x00 |
#define | C3DHALL5_CFG_B_INT_ON_DATA_OFF 0x08 |
#define | C3DHALL5_CFG_B_SET_PULSE_63_ODR 0x00 |
#define | C3DHALL5_CFG_B_SET_PULSE_PD_CONDITION 0x04 |
#define | C3DHALL5_CFG_B_OFFSET_ENABLE 0x02 |
#define | C3DHALL5_CFG_B_OFFSET_DISABLE 0x00 |
#define | C3DHALL5_CFG_B_LPF_DISABLE_ODR_2 0x00 |
#define | C3DHALL5_CFG_B_LPF_ENABLE_ODR_4 0x01 |
#define C3DHALL5_CFG_B_INT_ON_DATA_OFF 0x08 |
#define C3DHALL5_CFG_B_LPF_DISABLE_ODR_2 0x00 |
#define C3DHALL5_CFG_B_LPF_ENABLE_ODR_4 0x01 |
#define C3DHALL5_CFG_B_OFFSET_DISABLE 0x00 |
#define C3DHALL5_CFG_B_OFFSET_ENABLE 0x02 |
#define C3DHALL5_CFG_B_OFFSET_IN_SINGLE_MODE_DISABLE 0x00 |
#define C3DHALL5_CFG_B_OFFSET_IN_SINGLE_MODE_ENABLE 0x10 |
#define C3DHALL5_CFG_B_SET_PULSE_63_ODR 0x00 |
#define C3DHALL5_CFG_B_SET_PULSE_PD_CONDITION 0x04 |