Macros
#define	C3DHALL5_REG_OFFSET_X_LSB 0x45

#define	C3DHALL5_REG_OFFSET_X_MSB 0x46

#define	C3DHALL5_REG_OFFSET_Y_LSB 0x47

#define	C3DHALL5_REG_OFFSET_Y_MSB 0x48

#define	C3DHALL5_REG_OFFSET_Z_LSB 0x49

#define	C3DHALL5_REG_OFFSET_Z_MSB 0x4A

#define	C3DHALL5_REG_WHO_AM_I 0x4F

#define	C3DHALL5_REG_CONFIG_A 0x60

#define	C3DHALL5_REG_CONFIG_B 0x61

#define	C3DHALL5_REG_CONFIG_C 0x62

#define	C3DHALL5_REG_INT_CTRL 0x63

#define	C3DHALL5_REG_INT_SOURCE 0x64

#define	C3DHALL5_REG_INT_THS_LSB 0x65

#define	C3DHALL5_REG_INT_THS_MSB 0x66

#define	C3DHALL5_REG_STATUS 0x67

#define	C3DHALL5_REG_X_AXIS_LSB 0x68

#define	C3DHALL5_REG_X_AXIS_MSB 0x69

#define	C3DHALL5_REG_Y_AXIS_LSB 0x6A

#define	C3DHALL5_REG_Y_AXIS_MSB 0x6B

#define	C3DHALL5_REG_Z_AXIS_LSB 0x6C

#define	C3DHALL5_REG_Z_AXIS_MSB 0x6D

#define	C3DHALL5_REG_TEMP_LSB 0x6E

#define	C3DHALL5_REG_TEMP_MSB 0x6F

Detailed Description

Macro Definition Documentation

◆ C3DHALL5_REG_CONFIG_A

#define C3DHALL5_REG_CONFIG_A 0x60

◆ C3DHALL5_REG_CONFIG_B

#define C3DHALL5_REG_CONFIG_B 0x61

◆ C3DHALL5_REG_CONFIG_C

#define C3DHALL5_REG_CONFIG_C 0x62

◆ C3DHALL5_REG_INT_CTRL

#define C3DHALL5_REG_INT_CTRL 0x63

◆ C3DHALL5_REG_INT_SOURCE

#define C3DHALL5_REG_INT_SOURCE 0x64

◆ C3DHALL5_REG_INT_THS_LSB

#define C3DHALL5_REG_INT_THS_LSB 0x65

◆ C3DHALL5_REG_INT_THS_MSB

#define C3DHALL5_REG_INT_THS_MSB 0x66

◆ C3DHALL5_REG_OFFSET_X_LSB

#define C3DHALL5_REG_OFFSET_X_LSB 0x45

◆ C3DHALL5_REG_OFFSET_X_MSB

#define C3DHALL5_REG_OFFSET_X_MSB 0x46

◆ C3DHALL5_REG_OFFSET_Y_LSB

#define C3DHALL5_REG_OFFSET_Y_LSB 0x47

◆ C3DHALL5_REG_OFFSET_Y_MSB

#define C3DHALL5_REG_OFFSET_Y_MSB 0x48

◆ C3DHALL5_REG_OFFSET_Z_LSB

#define C3DHALL5_REG_OFFSET_Z_LSB 0x49

◆ C3DHALL5_REG_OFFSET_Z_MSB

#define C3DHALL5_REG_OFFSET_Z_MSB 0x4A

◆ C3DHALL5_REG_STATUS

#define C3DHALL5_REG_STATUS 0x67

◆ C3DHALL5_REG_TEMP_LSB

#define C3DHALL5_REG_TEMP_LSB 0x6E

◆ C3DHALL5_REG_TEMP_MSB

#define C3DHALL5_REG_TEMP_MSB 0x6F

◆ C3DHALL5_REG_WHO_AM_I

#define C3DHALL5_REG_WHO_AM_I 0x4F

◆ C3DHALL5_REG_X_AXIS_LSB

#define C3DHALL5_REG_X_AXIS_LSB 0x68

◆ C3DHALL5_REG_X_AXIS_MSB

#define C3DHALL5_REG_X_AXIS_MSB 0x69

◆ C3DHALL5_REG_Y_AXIS_LSB

#define C3DHALL5_REG_Y_AXIS_LSB 0x6A

◆ C3DHALL5_REG_Y_AXIS_MSB

#define C3DHALL5_REG_Y_AXIS_MSB 0x6B

◆ C3DHALL5_REG_Z_AXIS_LSB

#define C3DHALL5_REG_Z_AXIS_LSB 0x6C

◆ C3DHALL5_REG_Z_AXIS_MSB

#define C3DHALL5_REG_Z_AXIS_MSB 0x6D

Macros