Macros
#define	C9DOF3_REG_ACC_WHO_AM_I 0x00

#define	C9DOF3_REG_ACC_DATA_START 0x02

#define	C9DOF3_REG_ACC_D_X_LSB 0x02

#define	C9DOF3_REG_ACC_D_X_MSB 0x03

#define	C9DOF3_REG_ACC_D_Y_LSB 0x04

#define	C9DOF3_REG_ACC_D_Y_MSB 0x05

#define	C9DOF3_REG_ACC_D_Z_LSB 0x06

#define	C9DOF3_REG_ACC_D_Z_MSB 0x07

#define	C9DOF3_REG_ACC_D_TEMP 0x08

#define	C9DOF3_REG_ACC_INT_STATUS_0 0x09

#define	C9DOF3_REG_ACC_INT_STATUS_1 0x0A

#define	C9DOF3_REG_ACC_INT_STATUS_2 0x0B

#define	C9DOF3_REG_ACC_INT_STATUS_3 0x0C

#define	C9DOF3_REG_ACC_FIFO_STATUS 0x0E

#define	C9DOF3_REG_ACC_PMU_RANGE 0x0F

#define	C9DOF3_REG_ACC_PMU_BW 0x10

#define	C9DOF3_REG_ACC_PMU_LPW 0x11

#define	C9DOF3_REG_ACC_PMU_LOW_POWER 0x12

#define	C9DOF3_REG_ACC_D_HBW 0x13

#define	C9DOF3_REG_ACC_BGW_SOFTRESET 0x14

#define	C9DOF3_REG_ACC_INT_EN_0 0x16

#define	C9DOF3_REG_ACC_INT_EN_1 0x17

#define	C9DOF3_REG_ACC_INT_EN_2 0x18

#define	C9DOF3_REG_ACC_INT_MAP_0 0x19

#define	C9DOF3_REG_ACC_INT_MAP_1 0x1A

#define	C9DOF3_REG_ACC_INT_MAP_2 0x1B

#define	C9DOF3_REG_ACC_INT_SRC 0x1E

#define	C9DOF3_REG_ACC_INT_OUT_CTRL 0x20

#define	C9DOF3_REG_ACC_INT_RST_LATCH 0x21

#define	C9DOF3_REG_ACC_INT_0 0x22

#define	C9DOF3_REG_ACC_INT_1 0x23

#define	C9DOF3_REG_ACC_INT_2 0x24

#define	C9DOF3_REG_ACC_INT_3 0x25

#define	C9DOF3_REG_ACC_INT_4 0x26

#define	C9DOF3_REG_ACC_INT_5 0x27

#define	C9DOF3_REG_ACC_INT_6 0x28

#define	C9DOF3_REG_ACC_INT_7 0x29

#define	C9DOF3_REG_ACC_INT_8 0x2A

#define	C9DOF3_REG_ACC_INT_9 0x2B

#define	C9DOF3_REG_ACC_INT_A 0x2C

#define	C9DOF3_REG_ACC_INT_B 0x2D

#define	C9DOF3_REG_ACC_INT_C 0x2E

#define	C9DOF3_REG_ACC_INT_D 0x2F

#define	C9DOF3_REG_ACC_FIFO_CONFIG_0 0x30

#define	C9DOF3_REG_ACC_PMU_SELF_TEST 0x32

#define	C9DOF3_REG_ACC_TRIM_NVM_CTRL 0x33

#define	C9DOF3_REG_ACC_BGW_SPI3_WDT 0x34

#define	C9DOF3_REG_ACC_OFC_CTRL 0x36

#define	C9DOF3_REG_ACC_OFC_SETTING 0x37

#define	C9DOF3_REG_ACC_OFC_OFFSET_X 0x38

#define	C9DOF3_REG_ACC_OFC_OFFSET_Y 0x39

#define	C9DOF3_REG_ACC_OFC_OFFSET_Z 0x3A

#define	C9DOF3_REG_ACC_TRIM_GPO 0x3B

#define	C9DOF3_REG_ACC_TRIM_GP1 0x3C

#define	C9DOF3_REG_ACC_FIFO_CONFIG_1 0x3E

#define	C9DOF3_REG_ACC_FIFO_DATA 0x3F

Detailed Description

Macro Definition Documentation

◆ C9DOF3_REG_ACC_BGW_SOFTRESET

#define C9DOF3_REG_ACC_BGW_SOFTRESET 0x14

◆ C9DOF3_REG_ACC_BGW_SPI3_WDT

#define C9DOF3_REG_ACC_BGW_SPI3_WDT 0x34

◆ C9DOF3_REG_ACC_D_HBW

#define C9DOF3_REG_ACC_D_HBW 0x13

◆ C9DOF3_REG_ACC_D_TEMP

#define C9DOF3_REG_ACC_D_TEMP 0x08

◆ C9DOF3_REG_ACC_D_X_LSB

#define C9DOF3_REG_ACC_D_X_LSB 0x02

◆ C9DOF3_REG_ACC_D_X_MSB

#define C9DOF3_REG_ACC_D_X_MSB 0x03

◆ C9DOF3_REG_ACC_D_Y_LSB

#define C9DOF3_REG_ACC_D_Y_LSB 0x04

◆ C9DOF3_REG_ACC_D_Y_MSB

#define C9DOF3_REG_ACC_D_Y_MSB 0x05

◆ C9DOF3_REG_ACC_D_Z_LSB

#define C9DOF3_REG_ACC_D_Z_LSB 0x06

◆ C9DOF3_REG_ACC_D_Z_MSB

#define C9DOF3_REG_ACC_D_Z_MSB 0x07

◆ C9DOF3_REG_ACC_DATA_START

#define C9DOF3_REG_ACC_DATA_START 0x02

◆ C9DOF3_REG_ACC_FIFO_CONFIG_0

#define C9DOF3_REG_ACC_FIFO_CONFIG_0 0x30

◆ C9DOF3_REG_ACC_FIFO_CONFIG_1

#define C9DOF3_REG_ACC_FIFO_CONFIG_1 0x3E

◆ C9DOF3_REG_ACC_FIFO_DATA

#define C9DOF3_REG_ACC_FIFO_DATA 0x3F

◆ C9DOF3_REG_ACC_FIFO_STATUS

#define C9DOF3_REG_ACC_FIFO_STATUS 0x0E

◆ C9DOF3_REG_ACC_INT_0

#define C9DOF3_REG_ACC_INT_0 0x22

◆ C9DOF3_REG_ACC_INT_1

#define C9DOF3_REG_ACC_INT_1 0x23

◆ C9DOF3_REG_ACC_INT_2

#define C9DOF3_REG_ACC_INT_2 0x24

◆ C9DOF3_REG_ACC_INT_3

#define C9DOF3_REG_ACC_INT_3 0x25

◆ C9DOF3_REG_ACC_INT_4

#define C9DOF3_REG_ACC_INT_4 0x26

◆ C9DOF3_REG_ACC_INT_5

#define C9DOF3_REG_ACC_INT_5 0x27

◆ C9DOF3_REG_ACC_INT_6

#define C9DOF3_REG_ACC_INT_6 0x28

◆ C9DOF3_REG_ACC_INT_7

#define C9DOF3_REG_ACC_INT_7 0x29

◆ C9DOF3_REG_ACC_INT_8

#define C9DOF3_REG_ACC_INT_8 0x2A

◆ C9DOF3_REG_ACC_INT_9

#define C9DOF3_REG_ACC_INT_9 0x2B

◆ C9DOF3_REG_ACC_INT_A

#define C9DOF3_REG_ACC_INT_A 0x2C

◆ C9DOF3_REG_ACC_INT_B

#define C9DOF3_REG_ACC_INT_B 0x2D

◆ C9DOF3_REG_ACC_INT_C

#define C9DOF3_REG_ACC_INT_C 0x2E

◆ C9DOF3_REG_ACC_INT_D

#define C9DOF3_REG_ACC_INT_D 0x2F

◆ C9DOF3_REG_ACC_INT_EN_0

#define C9DOF3_REG_ACC_INT_EN_0 0x16

◆ C9DOF3_REG_ACC_INT_EN_1

#define C9DOF3_REG_ACC_INT_EN_1 0x17

◆ C9DOF3_REG_ACC_INT_EN_2

#define C9DOF3_REG_ACC_INT_EN_2 0x18

◆ C9DOF3_REG_ACC_INT_MAP_0

#define C9DOF3_REG_ACC_INT_MAP_0 0x19

◆ C9DOF3_REG_ACC_INT_MAP_1

#define C9DOF3_REG_ACC_INT_MAP_1 0x1A

◆ C9DOF3_REG_ACC_INT_MAP_2

#define C9DOF3_REG_ACC_INT_MAP_2 0x1B

◆ C9DOF3_REG_ACC_INT_OUT_CTRL

#define C9DOF3_REG_ACC_INT_OUT_CTRL 0x20

◆ C9DOF3_REG_ACC_INT_RST_LATCH

#define C9DOF3_REG_ACC_INT_RST_LATCH 0x21

◆ C9DOF3_REG_ACC_INT_SRC

#define C9DOF3_REG_ACC_INT_SRC 0x1E

◆ C9DOF3_REG_ACC_INT_STATUS_0

#define C9DOF3_REG_ACC_INT_STATUS_0 0x09

◆ C9DOF3_REG_ACC_INT_STATUS_1

#define C9DOF3_REG_ACC_INT_STATUS_1 0x0A

◆ C9DOF3_REG_ACC_INT_STATUS_2

#define C9DOF3_REG_ACC_INT_STATUS_2 0x0B

◆ C9DOF3_REG_ACC_INT_STATUS_3

#define C9DOF3_REG_ACC_INT_STATUS_3 0x0C

◆ C9DOF3_REG_ACC_OFC_CTRL

#define C9DOF3_REG_ACC_OFC_CTRL 0x36

◆ C9DOF3_REG_ACC_OFC_OFFSET_X

#define C9DOF3_REG_ACC_OFC_OFFSET_X 0x38

◆ C9DOF3_REG_ACC_OFC_OFFSET_Y

#define C9DOF3_REG_ACC_OFC_OFFSET_Y 0x39

◆ C9DOF3_REG_ACC_OFC_OFFSET_Z

#define C9DOF3_REG_ACC_OFC_OFFSET_Z 0x3A

◆ C9DOF3_REG_ACC_OFC_SETTING

#define C9DOF3_REG_ACC_OFC_SETTING 0x37

◆ C9DOF3_REG_ACC_PMU_BW

#define C9DOF3_REG_ACC_PMU_BW 0x10

◆ C9DOF3_REG_ACC_PMU_LOW_POWER

#define C9DOF3_REG_ACC_PMU_LOW_POWER 0x12

◆ C9DOF3_REG_ACC_PMU_LPW

#define C9DOF3_REG_ACC_PMU_LPW 0x11

◆ C9DOF3_REG_ACC_PMU_RANGE

#define C9DOF3_REG_ACC_PMU_RANGE 0x0F

◆ C9DOF3_REG_ACC_PMU_SELF_TEST

#define C9DOF3_REG_ACC_PMU_SELF_TEST 0x32

◆ C9DOF3_REG_ACC_TRIM_GP1

#define C9DOF3_REG_ACC_TRIM_GP1 0x3C

◆ C9DOF3_REG_ACC_TRIM_GPO

#define C9DOF3_REG_ACC_TRIM_GPO 0x3B

◆ C9DOF3_REG_ACC_TRIM_NVM_CTRL

#define C9DOF3_REG_ACC_TRIM_NVM_CTRL 0x33

◆ C9DOF3_REG_ACC_WHO_AM_I

#define C9DOF3_REG_ACC_WHO_AM_I 0x00

Macros