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canfd6 2.0.0.0
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CAN FD 6 Click MCAN interrupts. More...
#include <canfd6.h>
Data Fields | ||
| union { | ||
| uint32_t word | ||
| struct { | ||
| uint8_t RF0N: 1 | ||
| uint8_t RF0W: 1 | ||
| uint8_t RF0F: 1 | ||
| uint8_t RF0L: 1 | ||
| uint8_t RF1N: 1 | ||
| uint8_t RF1W: 1 | ||
| uint8_t RF1F: 1 | ||
| uint8_t RF1L: 1 | ||
| uint8_t HPM: 1 | ||
| uint8_t TC: 1 | ||
| uint8_t TCF: 1 | ||
| uint8_t TFE: 1 | ||
| uint8_t TEFN: 1 | ||
| uint8_t TEFW: 1 | ||
| uint8_t TEFF: 1 | ||
| uint8_t TEFL: 1 | ||
| uint8_t TSW: 1 | ||
| uint8_t MRAF: 1 | ||
| uint8_t TOO: 1 | ||
| uint8_t DRX: 1 | ||
| uint8_t BEC: 1 | ||
| uint8_t BEU: 1 | ||
| uint8_t ELO: 1 | ||
| uint8_t EP: 1 | ||
| uint8_t EW: 1 | ||
| uint8_t BO: 1 | ||
| uint8_t WDI: 1 | ||
| uint8_t PEA: 1 | ||
| uint8_t PED: 1 | ||
| uint8_t ARA: 1 | ||
| uint8_t reserved: 2 | ||
| } | ||
| }; | ||
CAN FD 6 Click MCAN interrupts.
Struct containing the MCAN interrupt bit field.
| union { ... } |
| uint8_t ARA |
IR[29] ARA: Access to reserved address.
| uint8_t BEC |
IR[20] BEC: MRAM Bit error corrected.
| uint8_t BEU |
IR[21] BEU: MRAM Bit error uncorrected.
| uint8_t BO |
IR[25] BO: Bus_off status changed.
| uint8_t DRX |
IR[19] DRX: Message stored to dedicated RX buffer.
| uint8_t ELO |
IR[22] ELO: Error logging overflow.
| uint8_t EP |
IR[23] EP: Error_passive status changed.
| uint8_t EW |
IR[24] EW: Error_warning status changed.
| uint8_t HPM |
IR[8] HPM: High priority message.
| uint8_t MRAF |
IR[17] MRAF: Message RAM access failure.
| uint8_t PEA |
IR[27] PEA Protocol Error in arbitration phase (nominal bit time used).
| uint8_t PED |
IR[28] PED: Protocol error in data phase (data bit time is used).
| uint8_t reserved |
IR[30:31] Reserved, not writable.
| uint8_t RF0F |
IR[2] RF0F: Rx FIFO 0 full.
| uint8_t RF0L |
IR[3] RF0L: Rx FIFO 0 message lost.
| uint8_t RF0N |
IR[0] RF0N: Rx FIFO 0 new message.
| uint8_t RF0W |
IR[1] RF0W: Rx FIFO 0 watermark reached.
| uint8_t RF1F |
IR[6] RF1F: Rx FIFO 1 full.
| uint8_t RF1L |
IR[7] RF1L: Rx FIFO 1 message lost.
| uint8_t RF1N |
IR[4] RF1N: Rx FIFO 1 new message.
| uint8_t RF1W |
IR[5] RF1W: RX FIFO 1 watermark reached.
| uint8_t TC |
IR[9] TC: Transmission completed.
| uint8_t TCF |
IR[10] TCF: Transmission cancellation finished.
| uint8_t TEFF |
IR[14] TEFF: Tx Event FIFO full.
| uint8_t TEFL |
IR[15] TEFL: Tx Event FIFO element lost.
| uint8_t TEFN |
IR[12] TEFN: Tx Event FIFO new entry.
| uint8_t TEFW |
IR[13] TEFW: Tx Event FIFO water mark reached.
| uint8_t TFE |
IR[11] TFE: Tx FIFO Empty.
| uint8_t TOO |
IR[18] TOO: Time out occurred.
| uint8_t TSW |
IR[16] TSW: Timestamp wrapped around.
| uint8_t WDI |
IR[26] WDI: MRAM Watchdog Interrupt.
| uint32_t word |
Full register represented as a 32-bit word.