eeram3.h

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/****************************************************************************
** Copyright (C) 2020 MikroElektronika d.o.o.
** Contact: https://www.mikroe.com/contact
**
** Permission is hereby granted, free of charge, to any person obtaining a copy
** of this software and associated documentation files (the "Software"), to deal
** in the Software without restriction, including without limitation the rights
** to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
** copies of the Software, and to permit persons to whom the Software is
** furnished to do so, subject to the following conditions:
** The above copyright notice and this permission notice shall be
** included in all copies or substantial portions of the Software.
**
** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
**  USE OR OTHER DEALINGS IN THE SOFTWARE.
****************************************************************************/
 
#ifndef EERAM3_H
#define EERAM3_H
 
#ifdef __cplusplus
extern "C"{
#endif
 
#ifdef PREINIT_SUPPORTED
#include "preinit.h"
#endif
 
#ifdef MikroCCoreVersion
    #if MikroCCoreVersion >= 1
        #include "delays.h"
    #endif
#endif
 
#include "drv_digital_out.h"
#include "drv_digital_in.h"
#include "drv_spi_master.h"
#include "spi_specifics.h"
 
#define EERAM3_OPCODE_WREN                   0x06
#define EERAM3_OPCODE_WRDI                   0x04
#define EERAM3_OPCODE_WRITE                  0x02
#define EERAM3_OPCODE_READ                   0x03
#define EERAM3_OPCODE_RDLSWA                 0x0A
#define EERAM3_OPCODE_SECURE_WRITE           0x12
#define EERAM3_OPCODE_SECURE_READ            0x13
#define EERAM3_OPCODE_WRSR                   0x01
#define EERAM3_OPCODE_RDSR                   0x05
#define EERAM3_OPCODE_STORE                  0x08
#define EERAM3_OPCODE_RECALL                 0x09
#define EERAM3_OPCODE_WRNUR                  0xC2
#define EERAM3_OPCODE_RDNUR                  0xC3
#define EERAM3_OPCODE_HIBERNATE              0xB9
 
 // eeram3_reg
 
#define EERAM3_RDY_BIT_MASK                  0x01
#define EERAM3_WEL_BIT_MASK                  0x02
#define EERAM3_BLOCK_PROTECT_BITS_MASK       0x0C
#define EERAM3_BLOCK_PROTECT_NONE            0x00
#define EERAM3_BLOCK_PROTECT_UPPER_QUARTER   0x04
#define EERAM3_BLOCK_PROTECT_UPPER_HALF      0x08
#define EERAM3_BLOCK_PROTECT_ALL             0x0C
#define EERAM3_SWM_BIT_MASK                  0x10
#define EERAM3_PRO_BIT_MASK                  0x20
#define EERAM3_ASE_BIT_MASK                  0x40
 
#define EERAM3_MIN_ADDRESS                   0x0000
#define EERAM3_MAX_ADDRESS                   0x7FFF
#define EERAM3_MAX_PAGE_ADDRESS              0x3F
 
#define EERAM3_SET_DATA_SAMPLE_EDGE      SET_SPI_DATA_SAMPLE_EDGE
#define EERAM3_SET_DATA_SAMPLE_MIDDLE    SET_SPI_DATA_SAMPLE_MIDDLE
 
 // eeram3_set
 
#define EERAM3_MAP_MIKROBUS( cfg, mikrobus ) \
    cfg.miso = MIKROBUS( mikrobus, MIKROBUS_MISO ); \
    cfg.mosi = MIKROBUS( mikrobus, MIKROBUS_MOSI ); \
    cfg.sck  = MIKROBUS( mikrobus, MIKROBUS_SCK ); \
    cfg.cs   = MIKROBUS( mikrobus, MIKROBUS_CS ); \
    cfg.hld = MIKROBUS( mikrobus, MIKROBUS_INT )
 
 // eeram3_map
 // eeram3
 
typedef struct
{
    // Output pins
    digital_out_t   hld;         
    // Modules
    spi_master_t    spi;         
    pin_name_t      chip_select; 
} eeram3_t;
 
typedef struct
{
    // Communication gpio pins
    pin_name_t  miso;                                   
    pin_name_t  mosi;                                   
    pin_name_t  sck;                                    
    pin_name_t  cs;                                     
    // Additional gpio pins
    pin_name_t  hld;                                    
    // static variable
    uint32_t                           spi_speed;       
    spi_master_mode_t                  spi_mode;        
    spi_master_chip_select_polarity_t  cs_polarity;     
} eeram3_cfg_t;
 
typedef enum
{
    EERAM3_OK = 0,
    EERAM3_ERROR = -1
 
} eeram3_return_value_t;
 
void eeram3_cfg_setup ( eeram3_cfg_t *cfg );
 
err_t eeram3_init ( eeram3_t *ctx, eeram3_cfg_t *cfg );
 
void eeram3_default_cfg ( eeram3_t *ctx );
 
err_t eeram3_write_opcode ( eeram3_t *ctx, uint8_t opcode );
 
err_t eeram3_read_opcode ( eeram3_t *ctx, uint8_t opcode, uint8_t *data_out, uint8_t len );
 
void eeram3_set_hld_pin ( eeram3_t *ctx, uint8_t state );
 
err_t eeram3_enable_write ( eeram3_t *ctx );
 
err_t eeram3_disable_write ( eeram3_t *ctx );
 
err_t eeram3_set_block_protection ( eeram3_t *ctx, uint8_t block_protect );
 
err_t eeram3_write_status ( eeram3_t *ctx, uint8_t status );
 
err_t eeram3_read_status ( eeram3_t *ctx, uint8_t *status );
 
err_t eeram3_enter_hibernate_mode ( eeram3_t *ctx );
 
void eeram3_wakeup_from_hibernate ( eeram3_t *ctx );
 
err_t eeram3_memory_write ( eeram3_t *ctx, uint16_t address, uint8_t *data_in, uint16_t len );
 
err_t eeram3_memory_read ( eeram3_t *ctx, uint16_t address, uint8_t *data_out, uint16_t len );
 
err_t eeram3_memory_secure_write ( eeram3_t *ctx, uint16_t address, uint8_t *data_in, uint8_t len );
 
err_t eeram3_memory_secure_read ( eeram3_t *ctx, uint16_t address, uint8_t *data_out, uint8_t len );
 
err_t eeram3_read_last_written_address ( eeram3_t *ctx, uint16_t *address );
 
err_t eeram3_nv_user_space_write ( eeram3_t *ctx, uint16_t data_in );
 
err_t eeram3_nv_user_space_read ( eeram3_t *ctx, uint16_t *data_out );
 
err_t eeram3_store_data ( eeram3_t *ctx );
 
err_t eeram3_recall_data ( eeram3_t *ctx );
 
err_t eeram3_autostore_enable ( eeram3_t *ctx );
 
err_t eeram3_autostore_disable ( eeram3_t *ctx );
 
#ifdef __cplusplus
}
#endif
#endif // EERAM3_H
 
 // eeram3
 
// ------------------------------------------------------------------------ END