enocean3.h

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/*
 * MikroSDK - MikroE Software Development Kit
 * Copyright© 2020 MikroElektronika d.o.o.
 * 
 * Permission is hereby granted, free of charge, to any person 
 * obtaining a copy of this software and associated documentation 
 * files (the "Software"), to deal in the Software without restriction, 
 * including without limitation the rights to use, copy, modify, merge, 
 * publish, distribute, sublicense, and/or sell copies of the Software, 
 * and to permit persons to whom the Software is furnished to do so, 
 * subject to the following conditions:
 * 
 * The above copyright notice and this permission notice shall be 
 * included in all copies or substantial portions of the Software.
 * 
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 
 * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
 * OR OTHER DEALINGS IN THE SOFTWARE. 
 */
 
// ----------------------------------------------------------------------------
 
#ifndef ENOCEAN3_H
#define ENOCEAN3_H
 
#ifdef PREINIT_SUPPORTED
#include "preinit.h"
#endif
 
#ifdef MikroCCoreVersion
    #if MikroCCoreVersion >= 1
        #include "delays.h"
    #endif
#endif
 
#include "drv_digital_out.h"
#include "drv_digital_in.h"
#include "drv_uart.h"
 
 
// -------------------------------------------------------------- PUBLIC MACROS 
#define ENOCEAN3_MAP_MIKROBUS( cfg, mikrobus ) \
  cfg.tx_pin  = MIKROBUS( mikrobus, MIKROBUS_TX ); \
  cfg.rx_pin  = MIKROBUS( mikrobus, MIKROBUS_RX ); \
  cfg.rst = MIKROBUS( mikrobus, MIKROBUS_RST )
 
#define ENOCEAN3_RETVAL  uint8_t
 
#define ENOCEAN3_OK           0x00
#define ENOCEAN3_INIT_ERROR   0xFF
#define DRV_RX_BUFFER_SIZE 500
#define DRV_TX_BUFFER_SIZE 100
#define ENOCEAN3_SYNC_BYTE                                  0x55
#define ENOCEAN3_MAX_BUFF_SIZE                              256
#define ENOCEAN3_HEADER_SIZE                                0x04
#define ENOCEAN3_BUFF_EMPTY                                 0x00
 
 
#define ENOCEAN3_RESPONSE_READY                             0x01
#define ENOCEAN3_RESPONSE_NOT_READY                         0x00
#define ENOCEAN3_UART_RX_READY                              0x01
#define ENOCEAN3_UART_RX_NOT_READY                          0x00
#define ENOCEAN3_OK                                         0x00
#define ENOCEAN3_INVALID_PACKET_SIZE                        0x01
              
#define ENOCEAN3_PACK_TYPE_EVENT                            0x04
#define ENOCEAN3_PACK_TYPE_COMMON_COMMAND                   0x05
#define ENOCEAN3_CO_EVENT_SECUREDEVICES                     0x05
#define ENOCEAN3_CO_WR_FILTER_ADD                           0x0B
#define ENOCEAN3_CO_WR_FILTER_ENABLE                        0x0E
#define ENOCEAN3_CO_WR_REPEATER                             0x09
#define ENOCEAN3_CO_SET_NOISETHRESHOLD                      0x32
 
#define ENOCEAN3_FILT_TYPE_SOURCE_ID                        0x00
#define ENOCEAN3_FILT_TYPE_R_ORG                            0x01
#define ENOCEAN3_FILT_TYPE_RSSI                             0x02
#define ENOCEAN3_FILT_TYPE_DEST_ID                          0x03
#define ENOCEAN3_FILT_KIND_NEG_TEL_FWRD                     0x00
#define ENOCEAN3_FILT_KIND_POS_TEL_FWRD                     0x80
#define ENOCEAN3_FILT_KIND_NEG_TEL_RPT                      0x40
#define ENOCEAN3_FILT_KIND_POS_TEL_RPT                      0xC0
#define ENOCEAN3_FILT_FWRD_OFF                              0x00
#define ENOCEAN3_FILT_FWRD_ON                               0x01
#define ENOCEAN3_FILT_OP_OR_ALL_FILT                        0x00
#define ENOCEAN3_FILT_OP_AND_ALL_FILT                       0x01
#define ENOCEAN3_FILT_OP_OR_RADIO_INTER_AND_FILT_RPT        0x08
#define ENOCEAN3_FILT_OP_AND_RADIO_INTER_OR_FILT_RPT        0x09
#define ENOCEAN3_RPT_OFF                                    0x00
#define ENOCEAN3_RPT_ALL_TELEG                              0x01
#define ENOCEAN3_RPT_SELECTIVE                              0x02
#define ENOCEAN3_RPT_LEVEL_OFF                              0x00
#define ENOCEAN3_RPT_LEVEL_ONE                              0x01
#define ENOCEAN3_RPT_LEVEL_TWO                              0x02
#define ENOCEAN3_RSSI_LEVEL_100_DBM_NEG                     0x2E
#define ENOCEAN3_RSSI_LEVEL_99_DBM_NEG                      0x2F
#define ENOCEAN3_RSSI_LEVEL_98_DBM_NEG                      0x30
#define ENOCEAN3_RSSI_LEVEL_97_DBM_NEG                      0x31
#define ENOCEAN3_RSSI_LEVEL_96_DBM_NEG                      0x32
#define ENOCEAN3_RSSI_LEVEL_95_DBM_NEG                      0x33
#define ENOCEAN3_RSSI_LEVEL_94_DBM_NEG                      0x34
#define ENOCEAN3_RSSI_LEVEL_93_DBM_NEG                      0x35
#define ENOCEAN3_RSSI_LEVEL_92_DBM_NEG                      0x36
#define ENOCEAN3_RSSI_LEVEL_91_DBM_NEG                      0x37
#define ENOCEAN3_RSSI_LEVEL_90_DBM_NEG                      0x38
 
 // End group macro 
// --------------------------------------------------------------- PUBLIC TYPES
                             /** @{ */
 
typedef struct {
 
    uint16_t   data_length;
    uint8_t    opt_length;
    uint8_t    packet_type;
    uint8_t    data_buff[ 256 ];
 
} enocean3_packet_t;
 
typedef void ( *enocean3_hdl_t )( enocean3_packet_t*, uint16_t* );
 
typedef struct
{
    // Output pins 
 
    digital_out_t rst;
    
    // Modules 
 
    uart_t uart;
 
    char uart_rx_buffer[ DRV_RX_BUFFER_SIZE ];
    char uart_tx_buffer[ DRV_TX_BUFFER_SIZE ];
 
    enocean3_hdl_t driver_hdl;
    uint8_t response_ready;
 
} enocean3_t;
 
typedef struct
{
    // Communication gpio pins 
 
    pin_name_t rx_pin;
    pin_name_t tx_pin;
    
    // Additional gpio pins 
 
    pin_name_t rst;
 
    // static variable 
 
    uint32_t          baud_rate;     // Clock speed.
    bool              uart_blocking;
    uart_data_bits_t  data_bit;      // Data bits.
    uart_parity_t     parity_bit;    // Parity bit.  
    uart_stop_bits_t  stop_bit;      // Stop bits.    
 
} enocean3_cfg_t;
 
typedef uint8_t enocean3_error_t;
 
 // End types group
 
// ----------------------------------------------- PUBLIC FUNCTION DECLARATIONS
 
#ifdef __cplusplus
extern "C"{
#endif
 
void enocean3_cfg_setup ( enocean3_cfg_t *cfg );
 
ENOCEAN3_RETVAL enocean3_init ( enocean3_t *ctx, enocean3_cfg_t *cfg );
 
void enocean3_set_rst_pin ( enocean3_t *ctx, uint8_t state );
 
void enocean3_generic_write ( enocean3_t *ctx, char *data_buf, uint16_t len );
 
int32_t enocean3_generic_read ( enocean3_t *ctx, char *data_buf, uint16_t max_len );
 
void enocean3_response_handler_set ( enocean3_t *ctx, enocean3_hdl_t handler );
 
uint8_t enocean3_send_packet( enocean3_t *ctx, enocean3_packet_t *packet );
 
uint8_t enocean3_response_ready( enocean3_t *ctx );
 
void enocean3_uart_isr( enocean3_t *ctx );
 
 
#ifdef __cplusplus
}
#endif
#endif  // _ENOCEAN3_H_
 
 // End public_function group
 
// ------------------------------------------------------------------------- END