ism.h

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/****************************************************************************
** Copyright (C) 2020 MikroElektronika d.o.o.
** Contact: https://www.mikroe.com/contact
**
** Permission is hereby granted, free of charge, to any person obtaining a copy
** of this software and associated documentation files (the "Software"), to deal
** in the Software without restriction, including without limitation the rights
** to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
** copies of the Software, and to permit persons to whom the Software is
** furnished to do so, subject to the following conditions:
** The above copyright notice and this permission notice shall be
** included in all copies or substantial portions of the Software.
**
** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
**  USE OR OTHER DEALINGS IN THE SOFTWARE.
****************************************************************************/
 
#ifndef ISM_H
#define ISM_H
 
#ifdef __cplusplus
extern "C"{
#endif
 
#ifdef PREINIT_SUPPORTED
#include "preinit.h"
#endif
 
#ifdef MikroCCoreVersion
    #if MikroCCoreVersion >= 1
        #include "delays.h"
    #endif
#endif
 
#include "drv_digital_out.h"
#include "drv_digital_in.h"
#include "drv_spi_master.h"
 
#define ISM_REG_BANK_0_CONFIG               0x00 
#define ISM_REG_BANK_0_EN_AA                0x01 
#define ISM_REG_BANK_0_EN_RXADDR            0x02 
#define ISM_REG_BANK_0_SETUP_AW             0x03 
#define ISM_REG_BANK_0_SETUP_RETR           0x04 
#define ISM_REG_BANK_0_RF_CH                0x05 
#define ISM_REG_BANK_0_RF_SETUP             0x06 
#define ISM_REG_BANK_0_STATUS               0x07 
#define ISM_REG_BANK_0_OBSERVE_TX           0x08 
#define ISM_REG_BANK_0_CD                   0x09 
#define ISM_REG_BANK_0_RX_ADDR_P0           0x0A 
#define ISM_REG_BANK_0_RX_ADDR_P1           0x0B 
#define ISM_REG_BANK_0_RX_ADDR_P2           0x0C 
#define ISM_REG_BANK_0_RX_ADDR_P3           0x0D 
#define ISM_REG_BANK_0_RX_ADDR_P4           0x0E 
#define ISM_REG_BANK_0_RX_ADDR_P5           0x0F 
#define ISM_REG_BANK_0_TX_ADDR              0x10 
#define ISM_REG_BANK_0_RX_PW_P0             0x11 
#define ISM_REG_BANK_0_RX_PW_P1             0x12 
#define ISM_REG_BANK_0_RX_PW_P2             0x13 
#define ISM_REG_BANK_0_RX_PW_P3             0x14 
#define ISM_REG_BANK_0_RX_PW_P4             0x15 
#define ISM_REG_BANK_0_RX_PW_P5             0x16 
#define ISM_REG_BANK_0_FIFO_STATUS          0x17 
#define ISM_REG_BANK_0_PAYLOAD_WIDTH        0x1F 
#define ISM_REG_BANK_1_REG_0                0x00 
#define ISM_REG_BANK_1_REG_1                0x01 
#define ISM_REG_BANK_1_REG_2                0x02 
#define ISM_REG_BANK_1_REG_3                0x03 
#define ISM_REG_BANK_1_REG_4                0x04 
#define ISM_REG_BANK_1_REG_5                0x05 
#define ISM_REG_BANK_1_REG_6                0x06 
#define ISM_REG_BANK_1_REG_7                0x07 
#define ISM_REG_BANK_1_REG_8                0x08 
#define ISM_REG_BANK_1_REG_9                0x09 
#define ISM_REG_BANK_1_REG_A                0x0A 
#define ISM_REG_BANK_1_REG_B                0x0B 
#define ISM_REG_BANK_1_REG_C                0x0C 
#define ISM_REG_BANK_1_REG_D                0x0D 
#define ISM_REG_BANK_1_REG_E                0x0E
 
 // ism_reg
 
#define ISM_CMD_FLUSH_TX                    0xE1  
#define ISM_CMD_FLUSH_RX                    0xE2  
#define ISM_CMD_REUSE_TX_PL                 0xE3  
#define ISM_CMD_W_TX_PAYLOAD_NOACK          0xB0
#define ISM_CMD_W_ACK_PAYLOAD               0xA8
#define ISM_CMD_ACTIVATE                    0x50
#define ISM_CMD_R_RX_PL_WID                 0x60
#define ISM_CMD_NOP_NOP                     0xFF 
 
 // ism_cmd
 
#define ISM_STATUS_RX_DR                    0x40
#define ISM_STATUS_TX_DS                    0x20
#define ISM_STATUS_MAX_RT                   0x10
#define STATUS_TX_FULL                      0x01
#define ISM_FIFO_STATUS_TX_REUSE            0x40
#define ISM_FIFO_STATUS_TX_FULL             0x20
#define ISM_FIFO_STATUS_TX_EMPTY            0x10
#define ISM_FIFO_STATUS_RX_FULL             0x02
#define ISM_FIFO_STATUS_RX_EMPTY            0x01
 
#define ISM_SEL_BANK_0                         0  
#define ISM_SEL_BANK_1                         1 
 
#define ISM_MAX_PACKET_LEN                    32
 
#define ISM_RT_PIN_STATE_LOW                   0
#define ISM_RT_PIN_STATE_HIGH                  1
 
#define ISM_RD_RX_PLOAD                     0x61  
#define ISM_WR_TX_PLOAD                     0xA0
 
#define ISM_READ_BIT_MASK                   0x00 
#define ISM_WRITE_BIT_MASK                  0x20
 
 // ism_set
 
#define ISM_MAP_MIKROBUS( cfg, mikrobus )           \
    cfg.miso = MIKROBUS( mikrobus, MIKROBUS_MISO ); \
    cfg.mosi = MIKROBUS( mikrobus, MIKROBUS_MOSI ); \
    cfg.sck  = MIKROBUS( mikrobus, MIKROBUS_SCK );  \
    cfg.cs   = MIKROBUS( mikrobus, MIKROBUS_CS );   \
    cfg.tl = MIKROBUS( mikrobus, MIKROBUS_AN );     \
    cfg.ce = MIKROBUS( mikrobus, MIKROBUS_RST );    \
    cfg.rl = MIKROBUS( mikrobus, MIKROBUS_PWM );    \
    cfg.irq = MIKROBUS( mikrobus, MIKROBUS_INT )
 
 // ism_map
 // ism
 
typedef struct
{
    // Output pins
    digital_out_t  tl;          
    digital_out_t  ce;          
    digital_out_t  rl;          
    // Input pins
    digital_in_t  irq;          
    // Modules
    spi_master_t  spi;          
    pin_name_t  chip_select;    
} ism_t;
 
typedef struct
{
    // Communication gpio pins
    pin_name_t  miso;           
    pin_name_t  mosi;           
    pin_name_t  sck;            
    pin_name_t  cs;             
    // Additional gpio pins
    pin_name_t  tl;             
    pin_name_t  ce;             
    pin_name_t  rl;             
    pin_name_t  irq;            
    // static variable
    uint32_t                           spi_speed;        
    spi_master_mode_t                  spi_mode;         
    spi_master_chip_select_polarity_t  cs_polarity;      
} ism_cfg_t;
 
typedef enum
{
   ISM_OK = 0,
   ISM_ERROR = -1
 
} ism_return_value_t;
 
void ism_cfg_setup ( ism_cfg_t *cfg );
 
err_t ism_init ( ism_t *ctx, ism_cfg_t *cfg );
 
void ism_default_cfg ( ism_t *ctx );
 
err_t ism_generic_write ( ism_t *ctx, uint8_t reg, uint8_t *data_in, uint8_t len );
 
err_t ism_generic_read ( ism_t *ctx, uint8_t reg, uint8_t *data_out, uint8_t len );
 
err_t ism_set_cmd ( ism_t *ctx, uint8_t cmd, uint8_t cmd_data );
 
void ism_chip_enable ( ism_t *ctx );
 
void ism_chip_disable ( ism_t *ctx );
 
void ism_set_rl_pin_state ( ism_t *ctx, uint8_t rt_pin_state );
 
void ism_set_tl_pin_state ( ism_t *ctx, uint8_t tl_pin_state );
 
uint8_t ism_check_interrupt_request ( ism_t *ctx );
 
err_t ism_switch_bank ( ism_t *ctx, uint8_t bank_sel );
 
err_t ism_switch_rx_mode ( ism_t *ctx );
 
err_t ism_switch_tx_mode ( ism_t *ctx );
 
err_t ism_device_config ( ism_t *ctx );
 
err_t ism_receive_packet ( ism_t *ctx, uint8_t *rx_data );
 
err_t ism_transmit_packet ( ism_t *ctx, uint8_t type, uint8_t *tx_data, uint8_t len );
 
#ifdef __cplusplus
}
#endif
#endif // ISM_H
 
 // ism
 
// ------------------------------------------------------------------------ END