loadcell3.h

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/****************************************************************************
** Copyright (C) 2020 MikroElektronika d.o.o.
** Contact: https://www.mikroe.com/contact
**
** Permission is hereby granted, free of charge, to any person obtaining a copy
** of this software and associated documentation files (the "Software"), to deal
** in the Software without restriction, including without limitation the rights
** to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
** copies of the Software, and to permit persons to whom the Software is
** furnished to do so, subject to the following conditions:
** The above copyright notice and this permission notice shall be
** included in all copies or substantial portions of the Software.
**
** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
**  USE OR OTHER DEALINGS IN THE SOFTWARE.
****************************************************************************/
 
#ifndef LOADCELL3_H
#define LOADCELL3_H
 
#ifdef __cplusplus
extern "C"{
#endif
 
#ifdef PREINIT_SUPPORTED
#include "preinit.h"
#endif
 
#ifdef MikroCCoreVersion
    #if MikroCCoreVersion >= 1
        #include "delays.h"
    #endif
#endif
 
#include "drv_digital_out.h"
#include "drv_digital_in.h"
#include "drv_i2c_master.h"
 
    
#define LOADCELL3_REG_TEST_MICRO_INTERFACE_CONTROL        0x0C
#define LOADCELL3_REG_TEST_PADC_DATA_1                    0x10
#define LOADCELL3_REG_TEST_PADC_DATA_2                    0x11
#define LOADCELL3_REG_TEST_TADC_DATA_1                    0x14
#define LOADCELL3_REG_TEST_TADC_DATA_2                    0x15
 
#define LOADCELL3_REG_CTRL_STATUS_PSMON_1                 0x58
#define LOADCELL3_REG_CTRL_STATUS_AFEDIAG                 0x5A 
#define LOADCELL3_REG_CTRL_STATUS_P_GAIN_SELECT           0x47
#define LOADCELL3_REG_CTRL_STATUS_T_GAIN_SELECT           0x48 
#define LOADCELL3_REG_CTRL_STATUS_TEMP_CTRL               0x4C 
#define LOADCELL3_REG_CTRL_STATUS_OFFSET_CANCEL           0x4E 
#define LOADCELL3_REG_CTRL_STATUS_DAC_REG0_1              0x30 
#define LOADCELL3_REG_CTRL_STATUS_DAC_REG0_2              0x31 
#define LOADCELL3_REG_CTRL_STATUS_OP_STAGE_CTRL           0x3B
    
#define LOADCELL3_REG_EEPROM_ARRAY_START                  0x00
#define LOADCELL3_REG_EEPROM_ARRAY_END                    0x7F
#define LOADCELL3_REG_EEPROM_CACHE_BYTE_0                 0x80
#define LOADCELL3_REG_EEPROM_CACHE_BYTE_1                 0x81
#define LOADCELL3_REG_EEPROM_PAGE_ADDRESS                 0x82
#define LOADCELL3_REG_EEPROM_CTRL                         0x83
#define LOADCELL3_REG_EEPROM_CRC                          0x84
#define LOADCELL3_REG_EEPROM_STATUS                       0x85
#define LOADCELL3_REG_EEPROM_CRC_STATUS                   0x86
#define LOADCELL3_REG_EEPROM_CRC_VALUE                    0x87
 
 // loadcell3_reg
 
#define LOADCELL3_SET_IF_SEL_ACCESSES_CONTROLLER          0x00
#define LOADCELL3_SET_IF_SEL_ACCESSES_DIGITAL_INTERFACE   0x01
    
#define LOADCELL3_SET_TSEM_MODE_SINGLE_ENDED              0x00
#define LOADCELL3_SET_TSEM_MODE_DIFFERENTIAL              0x01
      
#define LOADCELL3_SET_T_MUX_CTRL_EXT_TEMPE                0x00
#define LOADCELL3_SET_T_MUX_CTRL_TEST                     0x01
#define LOADCELL3_SET_T_MUX_CTRL_INT_TEMPE                0x02
#define LOADCELL3_SET_T_MUX_CTRL_BRIDGE_CURRENT           0x03
#define LOADCELL3_SET_T_MUX_CTRL_ITEMP                    0x04
    
#define LOADCELL3_SET_GAIN_1_33                           0x00
#define LOADCELL3_SET_GAIN_2                              0x01
#define LOADCELL3_SET_GAIN_4                              0x02
#define LOADCELL3_SET_GAIN_10                             0x03
#define LOADCELL3_SET_GAIN_20                             0x04
#define LOADCELL3_SET_GAIN_40                             0x05
#define LOADCELL3_SET_GAIN_100                            0x06
#define LOADCELL3_SET_GAIN_200                            0x07
    
#define LOADCELL3_SET_ITEMP_CTRL_50_mA                    0x00
#define LOADCELL3_SET_ITEMP_CTRL_100_mA                   0x01
#define LOADCELL3_SET_ITEMP_CTRL_200_mA                   0x02
#define LOADCELL3_SET_ITEMP_CTRL_1000_mA                  0x03
#define LOADCELL3_SET_ITEMP_CTRL_OFF                      0x04
    
#define LOADCELL3_SET_OFFSET_CANCEL_0_mV                  0x00
#define LOADCELL3_SET_OFFSET_CANCEL_3_65_mV               0x01
#define LOADCELL3_SET_OFFSET_CANCEL_7_3_mV                0x02
#define LOADCELL3_SET_OFFSET_CANCEL_10_95_mV              0x03
#define LOADCELL3_SET_OFFSET_CANCEL_14_6_mV               0x04
#define LOADCELL3_SET_OFFSET_CANCEL_18_28_mV              0x05
#define LOADCELL3_SET_OFFSET_CANCEL_21_9_mV               0x06
#define LOADCELL3_SET_OFFSET_CANCEL_25_55_mV              0x07
#define LOADCELL3_SET_OFFSET_CANCEL_29_2_mV               0x08
#define LOADCELL3_SET_OFFSET_CANCEL_32_85_mV              0x09
#define LOADCELL3_SET_OFFSET_CANCEL_36_5_mV               0x0A
#define LOADCELL3_SET_OFFSET_CANCEL_40_15_mV              0x0B
#define LOADCELL3_SET_OFFSET_CANCEL_43_8_mV               0x0C
#define LOADCELL3_SET_OFFSET_CANCEL_47_45_mV              0x0D
#define LOADCELL3_SET_OFFSET_CANCEL_51_1_mV               0x0E
#define LOADCELL3_SET_OFFSET_CANCEL_54_75_mV              0x0F
    
#define LOADCELL3_SET_OFFSET_CURRENT_VINPN                0x00
#define LOADCELL3_SET_OFFSET_CURRENT_VINPP                0x01
 
#define LOADCELL3_SET_DEV_ADDR                            0x42
#define LOADCELL3_SET_MEMORY_PAGE_TEST_REG                0x40
#define LOADCELL3_SET_MEMORY_PAGE_CONTROL_AND_STATUS_REG  0x42
#define LOADCELL3_SET_MEMORY_PAGE_EEPROM_CACHE_CELLS      0x45
#define LOADCELL3_SET_MEMORY_PAGE_CTRL_AND_STATUS_REG     0x47
 
 // loadcell3_set
 
#define LOADCELL3_WEIGHT_ZERO                               0
#define LOADCELL3_WEIGHT_100G                             100
#define LOADCELL3_WEIGHT_500G                             500
#define LOADCELL3_WEIGHT_1000G                           1000
#define LOADCELL3_WEIGHT_5000G                           5000
#define LOADCELL3_WEIGHT_10000G                         10000
 
 // weight
 
#define LOADCELL3_DATA_NO_DATA                              0
#define LOADCELL3_DATA_OK                                   1   
 
 // status
 
#define LOADCELL3_MAP_MIKROBUS( cfg, mikrobus )   \
    cfg.scl = MIKROBUS( mikrobus, MIKROBUS_SCL ); \
    cfg.sda = MIKROBUS( mikrobus, MIKROBUS_SDA ); \
    cfg.an = MIKROBUS( mikrobus, MIKROBUS_AN )
 
 // loadcell3_map
 // loadcell3
 
typedef struct
{
    // Input pins
 
    digital_in_t  an;         
    // Modules
 
    i2c_master_t i2c;         
    // I2C slave address
 
    uint8_t slave_address;    
} loadcell3_t;
 
typedef struct
{
    pin_name_t  scl;        
    pin_name_t  sda;        
    pin_name_t  an;         
    uint32_t  i2c_speed;    
    uint8_t   i2c_address;  
} loadcell3_cfg_t;
 
typedef enum
{
   LOADCELL3_OK = 0,
   LOADCELL3_ERROR = -1
 
} loadcell3_return_value_t;
 
typedef struct
{
    float tare;
    uint8_t tare_ok;
    float weight_coeff_100g;
    uint8_t weight_data_100g_ok;
    float weight_coeff_500g;
    uint8_t weight_data_500g_ok;
    float weight_coeff_1000g;
    uint8_t weight_data_1000g_ok;
    float weight_coeff_5000g;
    uint8_t weight_data_5000g_ok;
    float weight_coeff_10000g;
    uint8_t weight_data_10000g_ok;
}
loadcell3_data_t;
 
void loadcell3_cfg_setup ( loadcell3_cfg_t *cfg );
 
err_t loadcell3_init ( loadcell3_t *ctx, loadcell3_cfg_t *cfg );
 
err_t loadcell3_default_cfg ( loadcell3_t *ctx );
 
err_t loadcell3_generic_write ( loadcell3_t *ctx, uint8_t reg, uint8_t *tx_buf, uint8_t tx_len );
 
err_t loadcell3_generic_read ( loadcell3_t *ctx, uint8_t reg, uint8_t *rx_buf, uint8_t rx_len );
 
err_t loadcell3_generic_eeprom_write ( loadcell3_t *ctx, uint8_t reg, uint8_t *tx_buf, uint8_t tx_len );
 
err_t loadcell3_generic_eeprom_read ( loadcell3_t *ctx, uint8_t reg, uint8_t *rx_buf, uint8_t rx_len );
 
err_t loadcell3_generic_test_page_write ( loadcell3_t *ctx, uint8_t reg, uint8_t *tx_buf, uint8_t tx_len );
 
err_t loadcell3_generic_test_page_read ( loadcell3_t *ctx, uint8_t reg, uint8_t *rx_buf, uint8_t rx_len );
 
err_t loadcell3_set_memory_page_slave_addr ( loadcell3_t *ctx, uint8_t memory_page );
 
err_t loadcell3_accesses_controller ( loadcell3_t *ctx );
 
err_t loadcell3_accesses_digital_interface_control ( loadcell3_t *ctx );
 
err_t loadcell3_soft_reset ( loadcell3_t *ctx );
 
err_t loadcell3_set_p_gain ( loadcell3_t *ctx, uint8_t p_gain );
 
err_t loadcell3_set_t_gain ( loadcell3_t *ctx, uint8_t t_gain );
 
err_t loadcell3_set_temp_mode ( loadcell3_t *ctx, uint8_t t_mode );
 
err_t loadcell3_set_t_mux_ctrl ( loadcell3_t *ctx, uint8_t t_mux_ctrl );
 
err_t loadcell3_itemp_ctrl ( loadcell3_t *ctx, uint8_t itemp_ctrl );
 
err_t loadcell3_set_offset ( loadcell3_t *ctx, uint8_t offset_cancel_val, uint8_t offset_cancel_sel );
 
int16_t loadcell3_get_p_adc_data ( loadcell3_t *ctx );
 
int16_t loadcell3_get_t_adc_data ( loadcell3_t *ctx );
 
void loadcell3_tare ( loadcell3_t *ctx, loadcell3_data_t *cell_data );
 
err_t loadcell3_calibration ( loadcell3_t *ctx, uint16_t cal_val, loadcell3_data_t *cell_data );
 
float loadcell3_get_weight ( loadcell3_t *ctx, loadcell3_data_t *cell_data );
 
#ifdef __cplusplus
}
#endif
#endif // LOADCELL3_H
 
 // loadcell3
 
// ------------------------------------------------------------------------ END