This file contains API for MCP251863 Click Driver. More...

#include "drv_digital_out.h"
#include "drv_digital_in.h"
#include "drv_spi_master.h"
#include "spi_specifics.h"

Data Structures
struct	mcp251863_can_cfg_t
	MCP251863 Click CAN Configure. More...

struct	mcp251863_config_t
	MCP251863 Click CAN Message Configuration. More...

struct	mcp251863_msg_obj_id_t
	MCP251863 Click CAN Message Object ID. More...

struct	mcp251863_tx_msg_obj_ctl_t
	MCP251863 Click CAN TX Message Object Control. More...

union	mcp251863_tx_msg_obj_t
	MCP251863 Click CAN TX Message Object. More...

struct	mcp251863_rx_msg_obj_ctl_t
	MCP251863 Click CAN RX Message Object Control. More...

union	mcp251863_rx_msg_obj_t
	MCP251863 Click CAN RX Message Object. More...

union	mcp251863_tef_msg_obj_t
	MCP251863 Click CAN TEF Message Object. More...

struct	mcp251863_filt_obj_id_t
	MCP251863 Click CAN Filter Object ID. More...

union	mcp251863_filt_obj_t
	MCP251863 Click Filter Object Register. More...

struct	mcp251863_mask_obj_id_t
	MCP251863 Click CAN Mask Object ID. More...

union	mcp251863_mask_obj_t
	MCP251863 Click Mask Object Register. More...

union	mcp251863_reg_t

union	mcp251863_ctl_t
	MCP251863 Click CAN Control Register. More...

union	mcp251863_tx_que_ctl_t
	MCP251863 Click Transmit Queue Control Register. More...

union	mcp251863_tef_ctl_t
	MCP251863 Click Transmit Event FIFO Control Register. More...

union	mcp251863_fifo_ctl_t
	MCP251863 Click FIFO Control Register. More...

union	mcp251863_filt_ctl_t
	MCP251863 Click Filter Control Register. More...

union	mcp251863_osc_ctl_t
	MCP251863 Click Oscillator Control Register. More...

struct	mcp251863_div_ctl_t
	MCP251863 Click Oscillator Control. More...

union	mcp251863_io_ctl_t
	MCP251863 Click I/O Control Register. More...

union	mcp251863_ecc_ctl_t
	MCP251863 Click ECC Control Register. More...

struct	T_MCP251863_cfg_t
	MCP251863 Click CAN Configure. More...

struct	mcp251863_tx_fifo_cfg_t
	MCP251863 Click CAN Transmit Channel Configure. More...

struct	mcp251863_tx_que_cfg_t
	MCP251863 Click CAN Transmit Queue Configure. More...

struct	mcp251863_rx_fifo_cfg_t
	MCP251863 Click CAN Receive Channel Configure. More...

union	mcp251863_fifo_user_cfg_t
	MCP251863 Click FIFO User Address Register. More...

struct	mcp251863_tef_cfg_t
	MCP251863 Click CAN Transmit Event FIFO Configure. More...

union	mcp251863_nbt_cfg_t
	MCP251863 Click Nominal Bit Time Configuration Register. More...

union	mcp251863_dbt_cfg_t
	MCP251863 Click Data Bit Time Configuration Register. More...

union	mcp251863_tdc_cfg_t
	MCP251863 Click Transmitter Delay Compensation Register. More...

union	mcp251863_ts_cfg_t
	MCP251863 Click Time Stamp Configuration Register. More...

struct	mcp251863_int_en_t
	MCP251863 Click Interrupt Enables. More...

union	mcp251863_int_cfg_t
	MCP251863 Click Interrupt Configuration. More...

union	mcp251863_int_vec_t
	MCP251863 Click Interrupt Vector Register. More...

struct	mcp251863_int_flags_stat_t
	MCP251863 Click Interrupt Flags. More...

union	mcp251863_int_flag_t
	MCP251863 Click Interrupt Flag Register. More...

union	mcp251863_int_t
	MCP251863 Click Interrupt Register. More...

union	mcp251863_trec_t
	MCP251863 Click Transmit/Receive Error Count Register. More...

union	mcp251863_tef_t
	MCP251863 Click Transmit Event FIFO Status Register. More...

union	mcp251863_tx_que_stat_t
	MCP251863 Click Transmit Queue Status Register. More...

union	mcp251863_fifo_stat_t
	MCP251863 Click FIFO Status Register. More...

union	mcp251863_crc_t
	MCP251863 Click CRC Regsiter. More...

union	mcp251863_ecc_sta_t
	MCP251863 Click ECC Status Register. More...

struct	mcp251863_osc_sta_t
	MCP251863 Click Oscillator Status. More...

struct	mcp251863_bus_diag_flags_t
	MCP251863 Click CAN Bus Diagnostic flags. More...

struct	mcp251863_bus_error_count_t
	MCP251863 Click CAN Bus Diagnostic Error Counts. More...

union	mcp251863_bus_diag_t
	MCP251863 Click CAN BUS DIAGNOSTICS. More...

union	mcp251863_bus_diag0_t
	MCP251863 Click Diagnostic register 0. More...

union	mcp251863_bus_diag1_t
	MCP251863 Click Diagnostic register 1. More...

struct	mcp251863_func_data_t
	MCP251863 Click CAN message configuration. More...

struct	mcp251863_data_t
	MCP251863 Click CAN message configuration. More...

struct	mcp251863_t
	MCP251863 Click context object. More...

struct	mcp251863_cfg_t
	MCP251863 Click configuration object. More...

Macros
#define	MCP251863

#define	REV_B
	MCP251863 Revision.

#define	MCP251863_FIFO_08TO15_IMPLEMENTED
	MCP251863 Number of implemented FIFOs.

#define	MCP251863_FIFO_16TO31_IMPLEMENTED

#define	MCP251863_FILT_08TO15_IMPLEMENTED
	MCP251863 Number of implemented Filters.

#define	MCP251863_FILT_16TO31_IMPLEMENTED

#define	CAN_RESTRICTED_MODE_PRESENT
	MCP251863 Internal oscillator implemented.

#define	CAN_TXQUEUE_IMPLEMENTED
	MCP251863 Transmit Queue.

#define	N_MCP2518_CTRL_REGS 5
	MCP251863 Up to A1 silicon we had to multiply user address by 4.

#define	MCP251863_MAX_TXQUEUE_ATTEMPTS 50

#define	MCP251863_TX_REQUEST_ID 0x300

#define	MCP251863_TX_RESPONSE_ID 0x301

#define	MCP251863_CRCBASE 0xFFFF

#define	MCP251863_CRCUPPER 1

#define	MCP251863_DRV_CANFDSPI_INDEX_0 0

#define	MCP251863_SPI_DEFAULT_BUFFER_LENGTH 96

#define	MCP251863_ISO_CRC 1

#define	MCP251863_MAX_MSG_SIZE 76

#define	MCP251863_MAX_DATA_BYTES 64

#define	MCP251863_INS_RESET 0x00

#define	MCP251863_INS_READ 0x03

#define	MCP251863_INS_READ_CRC 0x0B

#define	MCP251863_INS_WRITE 0x02

#define	MCP251863_INS_WRITE_CRC 0x0A

#define	MCP251863_INS_WRITE_SAFE 0x0C

#define	MCP251863_FIFO_OFFSET ( 3 * 4 )

#define	MCP251863_FILTER_OFFSET ( 2 * 4 )

#define	MCP251863_REG_CITXQCON 0x050

#define	MCP251863_REG_CITXQSTA 0x054

#define	MCP251863_REG_CITXQUA 0x058

#define	MCP251863_REG_CIFLTCON ( MCP251863_REG_CIFIFOCON + ( MCP251863_FIFO_OFFSET * MCP251863_FIFO_TOTAL_CHANNELS ) )

#define	MCP251863_REG_CIFLTOBJ ( MCP251863_REG_CIFLTCON + MCP251863_FIFO_TOTAL_CHANNELS )

#define	MCP251863_REG_CIMASK ( MCP251863_REG_CIFLTOBJ + 4 )

#define	MCP251863_REG_OSC 0xE00

#define	MCP251863_REG_IOCON 0xE04

#define	MCP251863_REG_CRC 0xE08

#define	MCP251863_REG_ECCCON 0xE0C

#define	MCP251863_REG_ECCSTA 0xE10

#define	MCP251863_RAM_SIZE 2048

#define	MCP251863_RAMADDR_START 0x400

#define	MCP251863_RAMADDR_END ( MCP251863_RAMADDR_START + MCP251863_RAM_SIZE )

#define	MCP251863_LOW_POWER_MODE_EN 0x08

#define	MCP251863_LOW_POWER_MODE_DIS 0x00

#define	MCP251863_WAKEUP_INTERR_EN 0x40

#define	MCP251863_REG_CICON 0x000

#define	MCP251863_REG_CINBTCFG 0x004

#define	MCP251863_REG_CIDBTCFG 0x008

#define	MCP251863_REG_CITDC 0x00C

#define	MCP251863_REG_CITBC 0x010

#define	MCP251863_REG_CITSCON 0x014

#define	MCP251863_REG_CIVEC 0x018

#define	MCP251863_REG_CIINT 0x01C

#define	MCP251863_REG_CIINTFLAG MCP251863_REG_CIINT

#define	MCP251863_REG_CIINTENABLE ( MCP251863_REG_CIINT + 2 )

#define	MCP251863_REG_CIRXIF 0x020

#define	MCP251863_REG_CITXIF 0x024

#define	MCP251863_REG_CIRXOVIF 0x028

#define	MCP251863_REG_CITXATIF 0x02C

#define	MCP251863_REG_CITXREQ 0x030

#define	MCP251863_REG_CITREC 0x034

#define	MCP251863_REG_CIBDIAG0 0x038

#define	MCP251863_REG_CIBDIAG1 0x03C

#define	MCP251863_REG_CITEFCON 0x040

#define	MCP251863_REG_CITEFSTA 0x044

#define	MCP251863_REG_CITEFUA 0x048

#define	MCP251863_REG_CIFIFOBA 0x04C

#define	MCP251863_REG_CIFIFOCON 0x050

#define	MCP251863_REG_CIFIFOSTA 0x054

#define	MCP251863_REG_CIFIFOUA 0x058

#define	MCP251863_FIFO_CH0 0
	MCP251863 description setting.

#define	MCP251863_FIFO_CH1 1

#define	MCP251863_FIFO_CH2 2

#define	MCP251863_FIFO_CH3 3

#define	MCP251863_FIFO_CH4 4

#define	MCP251863_FIFO_CH5 5

#define	MCP251863_FIFO_CH6 6

#define	MCP251863_FIFO_CH7 7

#define	MCP251863_FIFO_CH8 8

#define	MCP251863_FIFO_CH9 9

#define	MCP251863_FIFO_CH10 10

#define	MCP251863_FIFO_CH11 11

#define	MCP251863_FIFO_CH12 12

#define	MCP251863_FIFO_CH13 13

#define	MCP251863_FIFO_CH14 14

#define	MCP251863_FIFO_CH15 15

#define	MCP251863_FIFO_CH16 16

#define	MCP251863_FIFO_CH17 17

#define	MCP251863_FIFO_CH18 18

#define	MCP251863_FIFO_CH19 19

#define	MCP251863_FIFO_CH20 20

#define	MCP251863_FIFO_CH21 21

#define	MCP251863_FIFO_CH22 22

#define	MCP251863_FIFO_CH23 23

#define	MCP251863_FIFO_CH24 24

#define	MCP251863_FIFO_CH25 25

#define	MCP251863_FIFO_CH26 26

#define	MCP251863_FIFO_CH27 27

#define	MCP251863_FIFO_CH28 28

#define	MCP251863_FIFO_CH29 29

#define	MCP251863_FIFO_CH30 30

#define	MCP251863_FIFO_CH31 31

#define	MCP251863_FIFO_TOTAL_CHANNELS 32

#define	MCP251863_FIFO_FIRST_CHANNEL MCP251863_FIFO_CH1

#define	CAN_TXQUEUE_CH0 MCP251863_FIFO_CH0

#define	MCP251863_FILT0 0
	MCP251863 CAN Filter Channels.

#define	MCP251863_FILT1 1

#define	MCP251863_FILT2 2

#define	MCP251863_FILT3 3

#define	MCP251863_FILT4 4

#define	MCP251863_FILT5 5

#define	MCP251863_FILT6 6

#define	MCP251863_FILT7 7

#define	MCP251863_FILT8 8

#define	MCP251863_FILT9 9

#define	MCP251863_FILT10 10

#define	MCP251863_FILT11 11

#define	MCP251863_FILT12 12

#define	MCP251863_FILT13 13

#define	MCP251863_FILT14 14

#define	MCP251863_FILT15 15

#define	MCP251863_FILT16 16

#define	MCP251863_FILT17 17

#define	MCP251863_FILT18 18

#define	MCP251863_FILT19 19

#define	MCP251863_FILT20 20

#define	MCP251863_FILT21 21

#define	MCP251863_FILT22 22

#define	MCP251863_FILT23 23

#define	MCP251863_FILT24 24

#define	MCP251863_FILT25 25

#define	MCP251863_FILT26 26

#define	MCP251863_FILT27 27

#define	MCP251863_FILT28 28

#define	MCP251863_FILT29 29

#define	MCP251863_FILT30 30

#define	MCP251863_FILT31 31

#define	MCP251863_FILT_TOTAL 32

#define	MCP251863_NORMAL_MODE 0x00
	MCP251863 CAN Operation Modes.

#define	MCP251863_SLEEP_MODE 0x01

#define	MCP251863_INT_LOOP_MODE 0x02

#define	MCP251863_LISTEN_ONLY_MODE 0x03

#define	MCP251863_CONFIG_MODE 0x04

#define	MCP251863_EXT_LOOP_MODE 0x05

#define	MCP251863_CLASSIC_MODE 0x06

#define	MCP251863_RESTRICT_MODE 0x07

#define	MCP251863_INVALID_MODE 0xFF

#define	MCP251863_TXBWS_NO_DELAY 0
	MCP251863 Transmit Bandwidth Sharing.

#define	MCP251863_TXBWS_2 1

#define	MCP251863_TXBWS_4 2

#define	MCP251863_TXBWS_8 3

#define	MCP251863_TXBWS_16 4

#define	MCP251863_TXBWS_32 5

#define	MCP251863_TXBWS_64 6

#define	MCP251863_TXBWS_128 7

#define	MCP251863_TXBWS_256 8

#define	MCP251863_TXBWS_512 9

#define	MCP251863_TXBWS_1024 10

#define	MCP251863_TXBWS_2048 11

#define	MCP251863_TXBWS_4096 12

#define	MCP251863_WFT00 0
	MCP251863 Wake-up Filter Time.

#define	MCP251863_WFT01 1

#define	MCP251863_WFT10 2

#define	MCP251863_WFT11 3

#define	MCP251863_DNET_FILT_DISABLE 0
	MCP251863 Data Byte Filter Number.

#define	MCP251863_DNET_FILT_SIZE_1_BIT 1

#define	MCP251863_DNET_FILT_SIZE_2_BIT 2

#define	MCP251863_DNET_FILT_SIZE_3_BIT 3

#define	MCP251863_DNET_FILT_SIZE_4_BIT 4

#define	MCP251863_DNET_FILT_SIZE_5_BIT 5

#define	MCP251863_DNET_FILT_SIZE_6_BIT 6

#define	MCP251863_DNET_FILT_SIZE_7_BIT 7

#define	MCP251863_DNET_FILT_SIZE_8_BIT 8

#define	MCP251863_DNET_FILT_SIZE_9_BIT 9

#define	MCP251863_DNET_FILT_SIZE_10_BIT 10

#define	MCP251863_DNET_FILT_SIZE_11_BIT 11

#define	MCP251863_DNET_FILT_SIZE_12_BIT 12

#define	MCP251863_DNET_FILT_SIZE_13_BIT 13

#define	MCP251863_DNET_FILT_SIZE_14_BIT 14

#define	MCP251863_DNET_FILT_SIZE_15_BIT 15

#define	MCP251863_DNET_FILT_SIZE_16_BIT 16

#define	MCP251863_DNET_FILT_SIZE_17_BIT 17

#define	MCP251863_DNET_FILT_SIZE_18_BIT 18

#define	MCP251863_PLSIZE_8 0
	MCP251863 FIFO Payload Size.

#define	MCP251863_PLSIZE_12 1

#define	MCP251863_PLSIZE_16 2

#define	MCP251863_PLSIZE_20 3

#define	MCP251863_PLSIZE_24 4

#define	MCP251863_PLSIZE_32 5

#define	MCP251863_PLSIZE_48 6

#define	MCP251863_PLSIZE_64 7

#define	MCP251863_DLC_0 0
	MCP251863 CAN Data Length Code.

#define	MCP251863_DLC_1 1

#define	MCP251863_DLC_2 2

#define	MCP251863_DLC_3 3

#define	MCP251863_DLC_4 4

#define	MCP251863_DLC_5 5

#define	MCP251863_DLC_6 6

#define	MCP251863_DLC_7 7

#define	MCP251863_DLC_8 8

#define	MCP251863_DLC_12 9

#define	MCP251863_DLC_16 10

#define	MCP251863_DLC_20 11

#define	MCP251863_DLC_24 12

#define	MCP251863_DLC_32 13

#define	MCP251863_DLC_48 14

#define	MCP251863_DLC_64 15

#define	MCP251863_RX_FIFO_EMPTY 0
	MCP251863 CAN RX FIFO Status.

#define	MCP251863_RX_FIFO_STATUS_MASK 0x0F

#define	MCP251863_RX_FIFO_NOT_EMPTY 0x01

#define	MCP251863_RX_FIFO_HALF_FULL 0x02

#define	MCP251863_RX_FIFO_FULL 0x04

#define	MCP251863_RX_FIFO_OVERFLOW 0x08

#define	MCP251863_TX_FIFO_FULL 0
	MCP251863 CAN TX FIFO Status.

#define	MCP251863_TX_FIFO_STATUS_MASK 0x1F7

#define	MCP251863_TX_FIFO_NOT_FULL 0x01

#define	MCP251863_TX_FIFO_HALF_FULL 0x02

#define	MCP251863_TX_FIFO_EMPTY 0x04

#define	MCP251863_TX_FIFO_ATTEMPTS_EXHAUSTED 0x10

#define	MCP251863_TX_FIFO_ERROR 0x20

#define	MCP251863_TX_FIFO_ARBITRATION_LOST 0x40

#define	MCP251863_TX_FIFO_ABORTED 0x80

#define	MCP251863_TX_FIFO_TRANSMITTING 0x100

#define	MCP251863_TEF_FIFO_EMPTY 0
	MCP251863 CAN TEF FIFO Status.

#define	MCP251863_TEF_FIFO_STATUS_MASK 0x0F

#define	MCP251863_TEF_FIFO_NOT_EMPTY 0x01

#define	MCP251863_TEF_FIFO_HALF_FULL 0x02

#define	MCP251863_TEF_FIFO_FULL 0x04

#define	MCP251863_TEF_FIFO_OVERFLOW 0x08

#define	MCP251863_TX_FIFO_NO_EVENT 0
	MCP251863 CAN Module Events.

#define	MCP251863_TX_FIFO_ALL_EVENTS 0x17

#define	MCP251863_TX_FIFO_NOT_FULL_EVENT 0x01

#define	MCP251863_TX_FIFO_HALF_FULL_EVENT 0x02

#define	MCP251863_TX_FIFO_EMPTY_EVENT 0x04

#define	MCP251863_TX_FIFO_ATTEMPTS_EXHAUSTED_EVENT 0x10

#define	MCP251863_RX_FIFO_NO_EVENT 0

#define	MCP251863_RX_FIFO_ALL_EVENTS 0x0F

#define	MCP251863_RX_FIFO_NOT_EMPTY_EVENT 0x01

#define	MCP251863_RX_FIFO_HALF_FULL_EVENT 0x02

#define	MCP251863_RX_FIFO_FULL_EVENT 0x04

#define	MCP251863_RX_FIFO_OVERFLOW_EVENT 0x08

#define	MCP251863_TEF_FIFO_NO_EVENT 0

#define	MCP251863_TEF_FIFO_ALL_EVENTS 0x0F

#define	MCP251863_TEF_FIFO_NOT_EMPTY_EVENT 0x01

#define	MCP251863_TEF_FIFO_HALF_FULL_EVENT 0x02

#define	MCP251863_TEF_FIFO_FULL_EVENT 0x04

#define	MCP251863_TEF_FIFO_OVERFLOW_EVENT 0x08

#define	MCP251863_NO_EVENT 0

#define	MCP251863_ALL_EVENTS 0xFF1F

#define	MCP251863_TX_EVENT 0x0001

#define	MCP251863_RX_EVENT 0x0002

#define	MCP251863_TIME_BASE_COUNTER_EVENT 0x0004

#define	MCP251863_OPERATION_MODE_CHANGE_EVENT 0x0008

#define	MCP251863_TEF_EVENT 0x0010

#define	MCP251863_RAM_ECC_EVENT 0x0100

#define	MCP251863_SPI_CRC_EVENT 0x0200

#define	MCP251863_TX_ATTEMPTS_EVENT 0x0400

#define	MCP251863_RX_OVERFLOW_EVENT 0x0800

#define	MCP251863_SYSTEM_ERROR_EVENT 0x1000

#define	MCP251863_BUS_ERROR_EVENT 0x2000

#define	MCP251863_BUS_WAKEUP_EVENT 0x4000

#define	MCP251863_RX_INVALID_MESSAGE_EVENT 0x8000

#define	MCP251863_500K_1M 0

#define	MCP251863_500K_2M 1

#define	MCP251863_500K_3M 2

#define	MCP251863_500K_4M 3

#define	MCP251863_500K_5M 4

#define	MCP251863_500K_6M7 5

#define	MCP251863_500K_8M 6

#define	MCP251863_500K_10M 7

#define	MCP251863_250K_500K 8

#define	MCP251863_250K_833K 9

#define	MCP251863_250K_1M 10

#define	MCP251863_250K_1M5 11

#define	MCP251863_250K_2M 12

#define	MCP251863_250K_3M 13

#define	MCP251863_250K_4M 14

#define	MCP251863_1000K_4M 15

#define	MCP251863_1000K_8M 16

#define	MCP251863_125K_500K 17

#define	MCP251863_NBT_125K 0

#define	MCP251863_NBT_250K 1

#define	MCP251863_NBT_500K 2

#define	MCP251863_NBT_1M 3

#define	MCP251863_DBT_500K 0

#define	MCP251863_DBT_833K 1

#define	MCP251863_DBT_1M 2

#define	MCP251863_DBT_1M5 3

#define	MCP251863_DBT_2M 4

#define	MCP251863_DBT_3M 5

#define	MCP251863_DBT_4M 6

#define	MCP251863_DBT_5M 7

#define	MCP251863_DBT_6M7 8

#define	MCP251863_DBT_8M 9

#define	MCP251863_DBT_10M 10

#define	MCP251863_SSP_MODE_OFF 0

#define	MCP251863_SSP_MODE_MANUAL 1

#define	MCP251863_SSP_MODE_AUTO 2

#define	MCP251863_ERROR_FREE_STATE 0

#define	MCP251863_ERROR_ALL 0x3F

#define	MCP251863_TX_RX_WARNING_STATE 0x01

#define	MCP251863_RX_WARNING_STATE 0x02

#define	MCP251863_TX_WARNING_STATE 0x04

#define	MCP251863_RX_BUS_PASSIVE_STATE 0x08

#define	MCP251863_TX_BUS_PASSIVE_STATE 0x10

#define	MCP251863_TX_BUS_OFF_STATE 0x20

#define	MCP251863_TS_SOF 0x00

#define	MCP251863_TS_EOF 0x01

#define	MCP251863_TS_RES 0x02

#define	MCP2518_ECC_NO_EVENT 0x00

#define	MCP2518_ECC_ALL_EVENTS 0x06

#define	MCP2518_ECC_SEC_EVENT 0x02

#define	MCP2518_ECC_DED_EVENT 0x04

#define	MCP251863_CRC_NO_EVENT 0x00

#define	MCP251863_CRC_ALL_EVENTS 0x03

#define	MCP251863_CRC_CRCERR_EVENT 0x01

#define	MCP251863_CRC_FORMERR_EVENT 0x02

#define	MCP251863_PIN_0 0
	MCP251863 Pin mode.

#define	MCP251863_PIN_1 1

#define	MCP251863_PINMODE_INT 0

#define	MCP251863_PINMODE_GPIO 1

#define	MCP251863_PINOUT 0

#define	MCP251863_PININ 1

#define	MCP251863_PINLOW 0

#define	MCP251863_PINHIGH 1

#define	MCP251863_PUSHPULL 0

#define	MCP251863_OPENDRAIN 1

#define	MCP251863_CLKO_CLOCK 0

#define	MCP251863_CLKO_SOF 1

#define	MCP251863_TXREQ_CH0 0x00000001
	MCP251863 TX req channel.

#define	MCP251863_TXREQ_CH1 0x00000002

#define	MCP251863_TXREQ_CH2 0x00000004

#define	MCP251863_TXREQ_CH3 0x00000008

#define	MCP251863_TXREQ_CH4 0x00000010

#define	MCP251863_TXREQ_CH5 0x00000020

#define	MCP251863_TXREQ_CH6 0x00000040

#define	MCP251863_TXREQ_CH7 0x00000080

#define	MCP251863_TXREQ_CH8 0x00000100

#define	MCP251863_TXREQ_CH9 0x00000200

#define	MCP251863_TXREQ_CH10 0x00000400

#define	MCP251863_TXREQ_CH11 0x00000800

#define	MCP251863_TXREQ_CH12 0x00001000

#define	MCP251863_TXREQ_CH13 0x00002000

#define	MCP251863_TXREQ_CH14 0x00004000

#define	MCP251863_TXREQ_CH15 0x00008000

#define	MCP251863_TXREQ_CH16 0x00010000

#define	MCP251863_TXREQ_CH17 0x00020000

#define	MCP251863_TXREQ_CH18 0x00040000

#define	MCP251863_TXREQ_CH19 0x00080000

#define	MCP251863_TXREQ_CH20 0x00100000

#define	MCP251863_TXREQ_CH21 0x00200000

#define	MCP251863_TXREQ_CH22 0x00400000

#define	MCP251863_TXREQ_CH23 0x00800000

#define	MCP251863_TXREQ_CH24 0x01000000

#define	MCP251863_TXREQ_CH25 0x02000000

#define	MCP251863_TXREQ_CH26 0x04000000

#define	MCP251863_TXREQ_CH27 0x08000000

#define	MCP251863_TXREQ_CH28 0x10000000

#define	MCP251863_TXREQ_CH29 0x20000000

#define	MCP251863_TXREQ_CH30 0x40000000

#define	MCP251863_TXREQ_CH31 0x80000000

#define	MCP251863_ICODE_FIFO_CH0 0
	MCP251863 FIFO channel.

#define	MCP251863_ICODE_FIFO_CH1 1

#define	MCP251863_ICODE_FIFO_CH2 2

#define	MCP251863_ICODE_FIFO_CH3 3

#define	MCP251863_ICODE_FIFO_CH4 4

#define	MCP251863_ICODE_FIFO_CH5 5

#define	MCP251863_ICODE_FIFO_CH6 6

#define	MCP251863_ICODE_FIFO_CH7 7

#define	MCP251863_ICODE_FIFO_CH8 8

#define	MCP251863_ICODE_FIFO_CH9 9

#define	MCP251863_ICODE_FIFO_CH10 10

#define	MCP251863_ICODE_FIFO_CH11 11

#define	MCP251863_ICODE_FIFO_CH12 12

#define	MCP251863_ICODE_FIFO_CH13 13

#define	MCP251863_ICODE_FIFO_CH14 14

#define	MCP251863_ICODE_FIFO_CH15 15

#define	MCP251863_ICODE_FIFO_CH16 16

#define	MCP251863_ICODE_FIFO_CH17 17

#define	MCP251863_ICODE_FIFO_CH18 18

#define	MCP251863_ICODE_FIFO_CH19 19

#define	MCP251863_ICODE_FIFO_CH20 20

#define	MCP251863_ICODE_FIFO_CH21 21

#define	MCP251863_ICODE_FIFO_CH22 22

#define	MCP251863_ICODE_FIFO_CH23 23

#define	MCP251863_ICODE_FIFO_CH24 24

#define	MCP251863_ICODE_FIFO_CH25 25

#define	MCP251863_ICODE_FIFO_CH26 26

#define	MCP251863_ICODE_FIFO_CH27 27

#define	MCP251863_ICODE_FIFO_CH28 28

#define	MCP251863_ICODE_FIFO_CH29 29

#define	MCP251863_ICODE_FIFO_CH30 30

#define	MCP251863_ICODE_FIFO_CH31 31

#define	MCP251863_ICODE_TOTAL_CHANNELS 32

#define	MCP251863_ICODE_NO_INT 64

#define	MCP251863_ICODE_CERRIF 65

#define	MCP251863_ICODE_WAKIF 66

#define	MCP251863_ICODE_RXOVIF 67

#define	MCP251863_ICODE_ADDRERR_SERRIF 68

#define	MCP251863_ICODE_MABOV_SERRIF 69

#define	MCP251863_ICODE_TBCIF 70

#define	MCP251863_ICODE_MODIF 71

#define	MCP251863_ICODE_IVMIF 72

#define	MCP251863_ICODE_TEFIF 73

#define	MCP251863_ICODE_TXATIF 74

#define	MCP251863_ICODE_RESERVED 75

#define	MCP251863_RXCODE_FIFO_CH0 0
	MCP251863 RX FIFO channel.

#define	MCP251863_RXCODE_FIFO_CH1 1

#define	MCP251863_RXCODE_FIFO_CH2 2

#define	MCP251863_RXCODE_FIFO_CH3 3

#define	MCP251863_RXCODE_FIFO_CH4 4

#define	MCP251863_RXCODE_FIFO_CH5 5

#define	MCP251863_RXCODE_FIFO_CH6 6

#define	MCP251863_RXCODE_FIFO_CH7 7

#define	MCP251863_RXCODE_FIFO_CH8 8

#define	MCP251863_RXCODE_FIFO_CH9 9

#define	MCP251863_RXCODE_FIFO_CH10 10

#define	MCP251863_RXCODE_FIFO_CH11 11

#define	MCP251863_RXCODE_FIFO_CH12 12

#define	MCP251863_RXCODE_FIFO_CH13 13

#define	MCP251863_RXCODE_FIFO_CH14 14

#define	MCP251863_RXCODE_FIFO_CH15 15

#define	MCP251863_RXCODE_FIFO_CH16 16

#define	MCP251863_RXCODE_FIFO_CH17 17

#define	MCP251863_RXCODE_FIFO_CH18 18

#define	MCP251863_RXCODE_FIFO_CH19 19

#define	MCP251863_RXCODE_FIFO_CH20 20

#define	MCP251863_RXCODE_FIFO_CH21 21

#define	MCP251863_RXCODE_FIFO_CH22 22

#define	MCP251863_RXCODE_FIFO_CH23 23

#define	MCP251863_RXCODE_FIFO_CH24 24

#define	MCP251863_RXCODE_FIFO_CH25 25

#define	MCP251863_RXCODE_FIFO_CH26 26

#define	MCP251863_RXCODE_FIFO_CH27 27

#define	MCP251863_RXCODE_FIFO_CH28 28

#define	MCP251863_RXCODE_FIFO_CH29 29

#define	MCP251863_RXCODE_FIFO_CH30 30

#define	MCP251863_RXCODE_FIFO_CH31 31

#define	MCP251863_RXCODE_TOTAL_CHANNELS 32

#define	MCP251863_RXCODE_NO_INT 64

#define	MCP251863_RXCODE_RESERVED 65

#define	MCP251863_TXCODE_FIFO_CH0 0
	MCP251863 TX FIFO channel.

#define	MCP251863_TXCODE_FIFO_CH1 1

#define	MCP251863_TXCODE_FIFO_CH2 2

#define	MCP251863_TXCODE_FIFO_CH3 3

#define	MCP251863_TXCODE_FIFO_CH4 4

#define	MCP251863_TXCODE_FIFO_CH5 5

#define	MCP251863_TXCODE_FIFO_CH6 6

#define	MCP251863_TXCODE_FIFO_CH7 7

#define	MCP251863_TXCODE_FIFO_CH8 8

#define	MCP251863_TXCODE_FIFO_CH9 9

#define	MCP251863_TXCODE_FIFO_CH10 10

#define	MCP251863_TXCODE_FIFO_CH11 11

#define	MCP251863_TXCODE_FIFO_CH12 12

#define	MCP251863_TXCODE_FIFO_CH13 13

#define	MCP251863_TXCODE_FIFO_CH14 14

#define	MCP251863_TXCODE_FIFO_CH15 15

#define	MCP251863_TXCODE_FIFO_CH16 16

#define	MCP251863_TXCODE_FIFO_CH17 17

#define	MCP251863_TXCODE_FIFO_CH18 18

#define	MCP251863_TXCODE_FIFO_CH19 19

#define	MCP251863_TXCODE_FIFO_CH20 20

#define	MCP251863_TXCODE_FIFO_CH21 21

#define	MCP251863_TXCODE_FIFO_CH22 22

#define	MCP251863_TXCODE_FIFO_CH23 23

#define	MCP251863_TXCODE_FIFO_CH24 24

#define	MCP251863_TXCODE_FIFO_CH25 25

#define	MCP251863_TXCODE_FIFO_CH26 26

#define	MCP251863_TXCODE_FIFO_CH27 27

#define	MCP251863_TXCODE_FIFO_CH28 28

#define	MCP251863_TXCODE_FIFO_CH29 29

#define	MCP251863_TXCODE_FIFO_CH30 30

#define	MCP251863_TXCODE_FIFO_CH31 31

#define	MCP251863_TXCODE_TOTAL_CHANNELS 32

#define	MCP251863_TXCODE_NO_INT 64

#define	MCP251863_TXCODE_RESERVED 65

#define	MCP251863_SYSCLK_40M 0
	MCP251863 system clock.

#define	MCP251863_SYSCLK_20M 1

#define	MCP251863_SYSCLK_10M 2

#define	MCP251863_CLKO_DIV1 0
	MCP251863 clock devider.

#define	MCP251863_CLKO_DIV2 1

#define	MCP251863_CLKO_DIV4 2

#define	MCP251863_CLKO_DIV10 3

#define	N_MCP251863_FIFO_REGS ( MCP251863_FIFO_TOTAL_CHANNELS * MCP251863_FIFO_OFFSET )

#define	N_MCP251863_FILT_CTRL_REGS ( MCP251863_FILT_TOTAL / 4 )

#define	N_MCP251863_FILT_OBJ_REGS ( MCP251863_FILT_TOTAL * MCP251863_FILTER_OFFSET )

#define	MCP251863_SET_DATA_SAMPLE_EDGE SET_SPI_DATA_SAMPLE_EDGE
	Data sample selection.

#define	MCP251863_SET_DATA_SAMPLE_MIDDLE SET_SPI_DATA_SAMPLE_MIDDLE

#define	MCP251863_MAP_MIKROBUS(cfg, mikrobus)
	MikroBUS pin mapping.

Typedefs
typedef uint8_t	mcp251863_id_t
	MCP251863 Click Module ID.

typedef uint32_t	mcp251863_msg_time_stamp_t
	MCP251863 Click CAN Message Time Stamp.

Enumerations
enum	mcp251863_return_value_t { MCP251863_OK = 0 , MCP251863_ERROR = -1 }
	MCP251863 Click return value data. More...

Functions
void	mcp251863_cfg_setup (mcp251863_cfg_t *cfg)
	MCP251863 configuration object setup function.

err_t	mcp251863_init (mcp251863_t ctx, mcp251863_cfg_t cfg)
	MCP251863 initialization function.

err_t	mcp251863_default_cfg (mcp251863_t *ctx)
	MCP251863 default configuration function.

err_t	mcp251863_generic_write (mcp251863_t ctx, uint8_t reg, uint8_t data_in, uint8_t len)
	MCP251863 data writing function.

err_t	mcp251863_generic_read (mcp251863_t ctx, uint8_t reg, uint8_t data_out, uint8_t len)
	MCP251863 data reading function.

err_t	mcp251863_transmit_message (mcp251863_t ctx, uint8_t data_in, uint16_t data_len)
	Message Transmit function.

err_t	mcp251863_receive_message (mcp251863_t ctx, uint8_t data_out, uint16_t *data_len)
	Message Receive function.

err_t	mcp251863_reset (mcp251863_t *ctx)
	Reset function.

err_t	mcp251863_read_byte (mcp251863_t ctx, uint16_t address, uint8_t data_out)
	SPI Read Byte function.

err_t	mcp251863_write_byte (mcp251863_t *ctx, uint16_t address, uint8_t data_in)
	SPI Write Byte.

err_t	mcp251863_read_word (mcp251863_t ctx, uint16_t address, uint32_t data_out)
	SPI Read Word.

err_t	mcp251863_write_word (mcp251863_t *ctx, uint16_t address, uint32_t data_in)
	SPI Write Word.

err_t	mcp251863_read_half_word (mcp251863_t ctx, uint16_t address, uint16_t data_out)
	SPI Read Half Word.

err_t	mcp251863_write_half_word (mcp251863_t *ctx, uint16_t address, uint16_t data_in)
	SPI Write Half Word.

err_t	mcp251863_write_byte_safe (mcp251863_t *ctx, uint16_t address, uint8_t data_in)
	SPI SFR Write Byte Safe.

err_t	mcp251863_write_word_safe (mcp251863_t *ctx, uint16_t address, uint32_t data_in)
	SPI RAM Write Word Safe.

err_t	mcp251863_read_byte_array (mcp251863_t ctx, uint16_t address, uint8_t data_out, uint16_t n_bytes)
	SPI Read Byte Array.

err_t	mcp251863_read_byte_array_with_crc (mcp251863_t ctx, bool from_ram, bool crc_is_correct)
	SPI Read Byte Array with CRC.

err_t	mcp251863_write_byte_array (mcp251863_t ctx, uint16_t address, uint8_t data_in, uint16_t n_bytes)
	SPI Write Byte Array.

err_t	mcp251863_write_byte_array_with_crc (mcp251863_t *ctx, bool from_ram)
	SPI Write Byte Array with CRC.

err_t	mcp251863_read_word_array (mcp251863_t ctx, uint16_t address, uint32_t data_out, uint16_t n_words)
	SPI Read Word Array.

err_t	mcp251863_write_word_array (mcp251863_t ctx, uint16_t address, uint32_t data_in, uint16_t n_words)
	SPI Write Word Array.

err_t	mcp251863_configure (mcp251863_t ctx, mcp251863_can_cfg_t config)
	CAN Control register configuration.

void	mcp251863_configure_object_reset (mcp251863_can_cfg_t *config)
	Reset Configure object to reset values.

err_t	mcp251863_operation_mode_select (mcp251863_t *ctx, uint8_t op_mode)
	Select Operation Mode.

err_t	mcp251863_operation_mode_get (mcp251863_t *ctx)
	Get Operation Mode.

err_t	mcp251863_transmit_channel_configure (mcp251863_t ctx, uint8_t channel, mcp251863_tx_fifo_cfg_t config)
	Configure Transmit FIFO.

void	mcp251863_transmit_channel_configure_object_reset (mcp251863_tx_fifo_cfg_t *config)
	Reset Transmit Channel Configure object to reset values.

err_t	mcp251863_transmit_queue_configure (mcp251863_t ctx, mcp251863_tx_que_cfg_t config)
	Configure Transmit Queue.

void	mcp251863_transmit_queue_configure_object_reset (mcp251863_tx_que_cfg_t *config)
	Reset Transmit Queue Configure object to reset values.

err_t	mcp251863_transmit_channel_load (mcp251863_t ctx, uint8_t channel, mcp251863_tx_msg_obj_t tx_obj, bool flush)
	TX Channel Load.

err_t	mcp251863_transmit_channel_flush (mcp251863_t *ctx, uint8_t channel)
	TX Channel Flush.

err_t	mcp251863_transmit_channel_status_get (mcp251863_t ctx, uint8_t channel, uint16_t status)
	Transmit Channel Status Get.

int8_t	mcp251863_transmit_channel_reset (mcp251863_t *ctx, uint8_t channel)
	Transmit FIFO Reset.

err_t	mcp251863_transmit_channel_update (mcp251863_t *ctx, uint8_t channel, bool flush)
	Transmit FIFO Update.

err_t	mcp251863_transmit_request_set (mcp251863_t *ctx, uint32_t tx_req)
	Request transmissions using TXREQ register.

err_t	mcp251863_transmit_request_get (mcp251863_t ctx, uint32_t tx_req)
	Get TXREQ register.

err_t	mcp251863_transmit_channel_abort (mcp251863_t *ctx, uint8_t channel)
	Abort transmission of single FIFO.

err_t	mcp251863_transmit_abort_all (mcp251863_t *ctx)
	Abort All transmissions.

err_t	mcp251863_transmit_band_width_sharing_set (mcp251863_t *ctx, uint8_t tx_bws)
	Set Transmit Bandwidth Sharing Delay.

err_t	mcp251863_filter_object_configure (mcp251863_t ctx, uint8_t filter, mcp251863_filt_obj_id_t id)
	Filter Object Configuration.

err_t	mcp251863_filter_mask_configure (mcp251863_t ctx, uint8_t filter, mcp251863_mask_obj_id_t mask)
	Filter Mask Configuration.

err_t	mcp251863_filter_to_fifo_link (mcp251863_t *ctx, uint8_t filter, uint8_t channel, bool enable)
	Link Filter to FIFO.

err_t	mcp251863_filter_enable (mcp251863_t *ctx, uint8_t filter)
	Filter Enable.

err_t	mcp251863_filter_disable (mcp251863_t *ctx, uint8_t filter)
	Filter Disable.

err_t	mcp251863_device_net_filter_count_set (mcp251863_t *ctx, uint8_t dnfc)
	Set Device Net Filter Count.

err_t	mcp251863_receive_channel_configure (mcp251863_t ctx, uint8_t channel, mcp251863_rx_fifo_cfg_t config)
	Configure Receive FIFO.

void	mcp251863_receive_channel_configure_object_reset (mcp251863_rx_fifo_cfg_t *config)
	Reset Receive Channel Configure object to reset value.

err_t	mcp251863_receive_channel_status_get (mcp251863_t ctx, uint8_t channel, uint8_t status)
	Receive Channel Status Get.

err_t	mcp251863_receive_message_get (mcp251863_t ctx, uint8_t channel, mcp251863_rx_msg_obj_t rx_obj)
	Get Received Message.

err_t	mcp251863_receive_channel_reset (mcp251863_t *ctx, uint8_t channel)
	Receive FIFO Reset.

err_t	mcp251863_receive_channel_update (mcp251863_t *ctx, uint8_t channel)
	Receive FIFO Update.

err_t	mcp251863_tef_status_get (mcp251863_t ctx, uint8_t status)
	Transmit Event FIFO Status Get.

err_t	mcp251863_tef_message_get (mcp251863_t ctx, mcp251863_tef_msg_obj_t tef_obj)
	Get Transmit Event FIFO Message.

err_t	mcp251863_tef_reset (mcp251863_t *ctx)
	Transmit Event FIFO Reset.

err_t	mcp251863_tef_update (mcp251863_t *ctx)
	Transmit Event FIFO Update.

err_t	mcp251863_tef_configure (mcp251863_t ctx, mcp251863_tef_cfg_t config)
	Configure Transmit Event FIFO.

void	mcp251863_tef_configure_object_reset (mcp251863_tef_cfg_t *config)
	Reset TefConfigure object to reset value.

err_t	mcp251863_module_event_get (mcp251863_t ctx, uint16_t flags)
	Module Event Get.

err_t	mcp251863_module_event_enable (mcp251863_t *ctx, uint16_t flags)
	Module Event Enable.

err_t	mcp251863_module_event_disable (mcp251863_t *ctx, uint16_t flags)
	Module Event Disable.

err_t	mcp251863_module_event_clear (mcp251863_t *ctx, uint16_t flags)
	Module Event Clear.

err_t	mcp251863_module_event_rx_code_get (mcp251863_t ctx, uint8_t rx_code)
	Get RX Code.

err_t	mcp251863_module_event_tx_code_get (mcp251863_t ctx, uint8_t tx_code)
	Get TX Code.

err_t	mcp251863_module_event_filter_hit_get (mcp251863_t ctx, uint8_t filter_hit)
	Get Filter Hit.

err_t	mcp251863_module_event_icode_get (mcp251863_t ctx, uint8_t icode)
	Get ICODE.

err_t	mcp251863_transmit_channel_event_get (mcp251863_t ctx, uint8_t channel, uint8_t flags)
	Transmit FIFO Event Get.

err_t	mcp251863_transmit_event_get (mcp251863_t ctx, uint32_t txif)
	Get pending interrupts of all transmit FIFOs.

err_t	mcp251863_transmit_event_attempt_get (mcp251863_t ctx, uint32_t txatif)
	Get pending TXATIF of all transmit FIFOs.

err_t	mcp251863_transmit_channel_index_get (mcp251863_t ctx, uint8_t channel, uint8_t idx)
	Transmit FIFO Index Get.

err_t	mcp251863_transmit_channel_event_enable (mcp251863_t *ctx, uint8_t channel, uint8_t flags)
	Transmit FIFO Event Enable.

err_t	mcp251863_transmit_channel_event_disable (mcp251863_t *ctx, uint8_t channel, uint8_t flags)
	Transmit FIFO Event Disable.

err_t	mcp251863_transmit_channel_event_attempt_clear (mcp251863_t *ctx, uint8_t channel)
	Transmit FIFO Event Clear.

err_t	mcp251863_receive_channel_event_get (mcp251863_t ctx, uint8_t channel, uint8_t flags)
	Receive FIFO Event Get.

err_t	mcp251863_receive_event_get (mcp251863_t ctx, uint32_t rxif)
	Get pending interrupts of all receive FIFOs.

err_t	mcp251863_receive_event_overflow_get (mcp251863_t ctx, uint32_t rxovif)
	Get pending RXOVIF of all receive FIFOs.

int8_t	mcp251863_receive_channel_index_get (mcp251863_t ctx, uint8_t channel, uint8_t idx)
	Receive FIFO Index Get.

err_t	mcp251863_receive_channel_event_enable (mcp251863_t *ctx, uint8_t channel, uint8_t flags)
	Receive FIFO Event Enable.

err_t	mcp251863_receive_channel_event_disable (mcp251863_t *ctx, uint8_t channel, uint8_t flags)
	Receive FIFO Event Disable.

err_t	mcp251863_receive_channel_event_overflow_clear (mcp251863_t *ctx, uint8_t channel)
	Receive FIFO Event Clear.

err_t	mcp251863_tef_event_get (mcp251863_t ctx, uint8_t flags)
	Transmit Event FIFO Event Get.

err_t	mcp251863_tef_event_enable (mcp251863_t *ctx, uint8_t flags)
	Transmit Event FIFO Event Enable.

err_t	mcp251863_tef_event_disable (mcp251863_t *ctx, uint8_t flags)
	Transmit Event FIFO Event Disable.

err_t	mcp251863_tef_event_overflow_clear (mcp251863_t *ctx)
	Transmit Event FIFO Event Clear.

err_t	mcp251863_error_count_transmit_get (mcp251863_t ctx, uint8_t tec)
	Transmit Error Count Get.

err_t	mcp251863_error_count_receive_get (mcp251863_t ctx, uint8_t rec)
	Receive Error Count Get.

err_t	mcp251863_error_state_get (mcp251863_t ctx, uint8_t flags)
	Error State Get.

err_t	mcp251863_error_count_state_get (mcp251863_t ctx, uint8_t tec, uint8_t rec, uint8_t flags)
	Error Counts and Error State Get.

err_t	mcp251863_bus_diagnostics_get (mcp251863_t ctx, mcp251863_bus_diag_t bus_diag)
	Get Bus Diagnostic Registers: all data_ at once, since we want to keep them in synch.

err_t	mcp251863_bus_diagnostics_clear (mcp251863_t *ctx)
	Clear Bus Diagnostic Registers.

err_t	mcp251863_ecc_enable (mcp251863_t *ctx)
	Enable ECC.

err_t	mcp251863_ecc_disable (mcp251863_t *ctx)
	Disable ECC.

err_t	mcp251863_ecc_event_get (mcp251863_t ctx, uint8_t flags)
	ECC Event Get.

err_t	mcp251863_ecc_parity_set (mcp251863_t *ctx, uint8_t parity)
	Set ECC Parity.

err_t	mcp251863_ecc_parity_get (mcp251863_t ctx, uint8_t parity)
	Get ECC Parity.

err_t	mcp251863_ecc_error_address_get (mcp251863_t ctx, uint16_t address)
	Get ECC Error Address.

err_t	mcp251863_ecc_event_enable (mcp251863_t *ctx, uint8_t flags)
	ECC Event Enable.

err_t	mcp251863_ecc_event_disable (mcp251863_t *ctx, uint8_t flags)
	ECC Event Disable.

err_t	mcp251863_ecc_event_clear (mcp251863_t *ctx, uint8_t flags)
	ECC Event Clear.

err_t	mcp251863_crc_event_enable (mcp251863_t *ctx, uint8_t flags)
	CRC Event Enable.

err_t	mcp251863_crc_event_disable (mcp251863_t *ctx, uint8_t flags)
	CRC Event Disnable.

err_t	mcp251863_crc_event_clear (mcp251863_t *ctx, uint8_t flags)
	CRC Event Clear.

err_t	mcp251863_crc_event_get (mcp251863_t ctx, uint8_t flags)
	CRC Event Get.

err_t	mcp251863_crc_value_get (mcp251863_t ctx, uint16_t crc)
	Get CRC Value from device.

err_t	mcp251863_ram_init (mcp251863_t *ctx, uint8_t rx_data)
	Initialize RAM.

err_t	mcp251863_time_stamp_enable (mcp251863_t *ctx)
	Time Stamp Enable.

err_t	mcp251863_time_stamp_disable (mcp251863_t *ctx)
	Time Stamp Disable.

err_t	mcp251863_time_stamp_get (mcp251863_t ctx, uint32_t time_stamp)
	Time Stamp Get.

err_t	mcp251863_time_stamp_set (mcp251863_t *ctx, uint32_t ts)
	Time Stamp Set.

err_t	mcp251863_time_stamp_mode_configure (mcp251863_t *ctx, uint8_t mode)
	Time Stamp Mode Configure.

err_t	mcp251863_time_stamp_prescaler_set (mcp251863_t *ctx, uint16_t time_stamp)
	Time Stamp Prescaler Set.

err_t	mcp251863_oscillator_enable (mcp251863_t *ctx)
	Enable oscillator to wake-up from sleep.

err_t	mcp251863_oscillator_control_set (mcp251863_t *ctx, mcp251863_div_ctl_t ctrl)
	Set Oscillator Control.

void	mcp251863_oscillator_control_object_reset (mcp251863_div_ctl_t *ctrl)
	Reset Oscillator Control.

err_t	mcp251863_oscillator_status_get (mcp251863_t ctx, mcp251863_osc_sta_t status)
	Get Oscillator Status.

err_t	mcp251863_bit_time_configure (mcp251863_t *ctx, uint8_t bit_time, uint8_t clk)
	Configure Bit Time registers (based on CAN clock speed).

err_t	mcp251863_bit_time_configure_nominal_40_mhz (mcp251863_t *ctx, uint8_t bit_time)
	Configure Nominal bit time for 40MHz system clock.

err_t	mcp251863_bit_time_configure_data_40_mhz (mcp251863_t *ctx, uint8_t bit_time)
	Configure Data bit time for 40MHz system clock.

err_t	mcp251863_bit_time_configure_nominal_20_mhz (mcp251863_t *ctx, uint8_t bit_time)
	Configure Nominal bit time for 20MHz system clock.

err_t	mcp251863_bit_time_configure_data_20_mhz (mcp251863_t *ctx, uint8_t bit_time)
	Configure Nominal bit time for 20MHz system clock.

err_t	mcp251863_bit_time_configure_nominal_10_mhz (mcp251863_t *ctx, uint8_t bit_time)
	Configure Nominal bit time for 10MHz system clock.

err_t	mcp251863_bit_time_configure_data_10_mhz (mcp251863_t *ctx, uint8_t bit_time)
	Configure Data bit time for 10MHz system clock.

err_t	mcp251863_gpio_mode_configure (mcp251863_t *ctx, uint8_t gpio0, uint8_t gpio1)
	Initialize GPIO Mode.

err_t	mcp251863_gpio_direction_configure (mcp251863_t *ctx, uint8_t gpio0, uint8_t gpio1)
	Initialize GPIO Direction.

err_t	mcp251863_gpio_standby_control_enable (mcp251863_t *ctx)
	Enable Transceiver Standby Control.

err_t	mcp251863_gpio_standby_control_disable (mcp251863_t *ctx)
	Disable Transceiver Standby Control.

err_t	mcp251863_gpio_interrupt_pins_open_drain_configure (mcp251863_t *ctx, uint8_t mode)
	Configure Open Drain Interrupts.

err_t	mcp251863_gpio_transmit_pin_open_drain_configure (mcp251863_t *ctx, uint8_t mode)
	Configure Open Drain TXCAN.

err_t	mcp251863_gpio_pin_set (mcp251863_t *ctx, uint8_t pos, uint8_t latch)
	GPIO Output Pin Set.

err_t	mcp251863_gpio_pin_read (mcp251863_t ctx, uint8_t pos, uint8_t state)
	Input Pin Read.

err_t	mcp251863_gpio_clock_output_configure (mcp251863_t *ctx, int8_t mode)
	Configure CLKO Pin.

uint32_t	mcp251863_dlc_to_data_bytes (uint8_t dlc)
	DLC to number of actual data_bytes conversion.

err_t	mcp251863_fifo_index_get (mcp251863_t ctx, uint8_t channel, uint8_t data_out)
	FIFO Index Get.

uint16_t	mcp251863_calculate_crc16 (uint8_t *data_pointer, uint16_t size)
	Calculate CRC16.

uint8_t	mcp251863_data_bytes_to_dlc (uint8_t num)
	Data bytes to DLC conversion.

Detailed Description

This file contains API for MCP251863 Click Driver.

Typedef Documentation

◆ mcp251863_id_t

typedef uint8_t mcp251863_id_t

MCP251863 Click Module ID.

Module ID definition of MCP251863 Click driver.

◆ mcp251863_msg_time_stamp_t

typedef uint32_t mcp251863_msg_time_stamp_t

MCP251863 Click CAN Message Time Stamp.

CAN Message Time Stamp definition of MCP251863 Click driver.

Enumeration Type Documentation

◆ mcp251863_return_value_t

enum mcp251863_return_value_t

MCP251863 Click return value data.

Predefined enum values for driver return values.

Enumerator
MCP251863_OK
MCP251863_ERROR

Data Structures

Macros

Typedefs