Instruction command set of MRAM 4 Click driver. More...

Macros
#define	MRAM4_CMD_RESET_ENABLE 0x66
	MRAM 4 description register.

#define	MRAM4_CMD_RESET_MEMORY 0x99

#define	MRAM4_CMD_READ_ID 0x9E

#define	MRAM4_CMD_READ_ID_MIO 0xAF

#define	MRAM4_CMD_READ 0x03

#define	MRAM4_CMD_READ_FAST_XIP 0x0B

#define	MRAM4_CMD_READ_FAST_DUAL_OUTPUT 0x3B

#define	MRAM4_CMD_READ_FAST_DUAL_IO 0xBB

#define	MRAM4_CMD_READ_FAST_QUAD_OUTPUT 0x6B

#define	MRAM4_CMD_READ_FAST_QUAD_IO 0xEB

#define	MRAM4_CMD_READ_FAST_DTR 0x0D

#define	MRAM4_CMD_READ_FAST_DUAL_OUTPUT_DTR 0x3D

#define	MRAM4_CMD_READ_FAST_DUAL_IO_DTR 0xBD

#define	MRAM4_CMD_READ_FAST_QUAD_OUTPUT_DTR 0x6D

#define	MRAM4_CMD_READ_FAST_QUAD_IO_DTR 0xED

#define	MRAM4_CMD_READ_WORD_QUAD_IO 0xE7

#define	MRAM4_CMD_READ_FAST_OCTAL_OUTPUT 0x8B

#define	MRAM4_CMD_READ_FAST_OCTAL_IO 0xCB

#define	MRAM4_CMD_READ_FAST_OCTAL_OUTPUT_DTR 0x9D

#define	MRAM4_CMD_READ_FAST_OCTAL_IO_DTR 0xFD

#define	MRAM4_CMD_READ_4BYTE_ADDR 0x13

#define	MRAM4_CMD_READ_FAST_4BYTE_ADDR 0x0C

#define	MRAM4_CMD_READ_FAST_DUAL_OUTPUT_4BYTE_ADDR 0x3C

#define	MRAM4_CMD_READ_FAST_DUAL_IO_4BYTE_ADDR 0xBC

#define	MRAM4_CMD_READ_FAST_QUAD_OUTPUT_4BYTE_ADDR 0x6C

#define	MRAM4_CMD_READ_FAST_QUAD_IO_4BYTE_ADDR 0xEC

#define	MRAM4_CMD_READ_FAST_DTR_4BYTE_ADDR 0x0E

#define	MRAM4_CMD_READ_FAST_DUAL_IO_DTR_4BYTE_ADDR 0xBE

#define	MRAM4_CMD_READ_FAST_QUAD_IO_DTR_4BYTE_ADDR 0xEE

#define	MRAM4_CMD_READ_FAST_OCTAL_OUTPUT_4BYTE_ADDR 0x7C

#define	MRAM4_CMD_READ_FAST_OCTAL_IO_4BYTE_ADDR 0xCC

#define	MRAM4_CMD_WRITE_ENABLE 0x06

#define	MRAM4_CMD_WRITE_DISABLE 0x04

#define	MRAM4_CMD_READ_STATUS_REG 0x05

#define	MRAM4_CMD_READ_FLAG_STATUS_REG 0x70

#define	MRAM4_CMD_READ_NVOL_CFG_REG 0xB5

#define	MRAM4_CMD_READ_VOL_CFG_REG 0x85

#define	MRAM4_CMD_READ_GENERAL_PURPOSE_READ_REG 0x96

#define	MRAM4_CMD_WRITE_STATUS_REG 0x01

#define	MRAM4_CMD_WRITE_NVOL_CFG_REG 0xB1

#define	MRAM4_CMD_WRITE_VOL_CFG_REG 0x81

#define	MRAM4_CMD_CLEAR_FLAG_STATUS_REG 0x50

#define	MRAM4_CMD_WRITE_PR_PAGE 0x02

#define	MRAM4_CMD_WRITE_PR_FAST_DUAL_INPUT 0xA2

#define	MRAM4_CMD_WRITE_PR_FAST_DUAL_INPUT_EXT 0xD2

#define	MRAM4_CMD_WRITE_PR_FAST_QUAD_INPUT 0x32

#define	MRAM4_CMD_WRITE_PR_FAST_QUAD_INPUT_EXT 0x38

#define	MRAM4_CMD_WRITE_PR_FAST_OCTAL_INPUT 0x82

#define	MRAM4_CMD_WRITE_PR_FAST_OCTAL_INPUT_EXT 0xC2

#define	MRAM4_CMD_WRITE_PR_4BYTE_ADDRESS 0x12

#define	MRAM4_CMD_WRITE_PR_FAST_QUAD_INPUT_4BYTE 0x34

#define	MRAM4_CMD_WRITE_PR_FAST_QUAD_INPUT_EXT_4BYTE 0x3E

#define	MRAM4_CMD_WRITE_PR_FAST_OCTAL_INPUT_4BYTE 0x84

#define	MRAM4_CMD_WRITE_FAST_OCTAL_INPUT_EXT_4BYTE 0x8E

#define	MRAM4_CMD_ERASE_32KB 0x52

#define	MRAM4_CMD_ERASE_4KB 0x20

#define	MRAM4_CMD_ERASE_SECTOR 0xD8

#define	MRAM4_CMD_ERASE_BULK_CHIP 0xC7

#define	MRAM4_CMD_ERASE_CHIP 0x60

#define	MRAM4_CMD_ERASE_SECTOR_4BYTE_ADDRESS 0xDC

#define	MRAM4_CMD_ERASE_4KB_4_BYTE_ADDRESS 0x21

#define	MRAM4_CMD_ERASE_32KB_4BYTE_ADDRESS 0x5C

#define	MRAM4_CMD_OTP_READ 0x4B

#define	MRAM4_CMD_OTP_WRITE 0x42

#define	MRAM4_CMD_4BYTE_ADDRESS_MODE_ENTER 0xB7

#define	MRAM4_CMD_4BYTE_ADDRESS_MODE_EXIT 0xE9

#define	MRAM4_CMD_DEEP_POWER_DOWN_ENTER 0xB9

#define	MRAM4_CMD_DEEP_POWER_DOWN_EXIT 0xAB

#define	MRAM4_CMD_INTERFACE_ACTIVATION_CRC 0x9B

#define	MRAM4_CMD_TDP_WRITE 0xF0

#define	MRAM4_CMD_TDP_READ 0xF1

#define	MRAM4_CMD_TDP_READ_DTR 0xF2

Detailed Description

Instruction command set of MRAM 4 Click driver.

Macro Definition Documentation

◆ MRAM4_CMD_4BYTE_ADDRESS_MODE_ENTER

#define MRAM4_CMD_4BYTE_ADDRESS_MODE_ENTER 0xB7

◆ MRAM4_CMD_4BYTE_ADDRESS_MODE_EXIT

#define MRAM4_CMD_4BYTE_ADDRESS_MODE_EXIT 0xE9

◆ MRAM4_CMD_CLEAR_FLAG_STATUS_REG

#define MRAM4_CMD_CLEAR_FLAG_STATUS_REG 0x50

◆ MRAM4_CMD_DEEP_POWER_DOWN_ENTER

#define MRAM4_CMD_DEEP_POWER_DOWN_ENTER 0xB9

◆ MRAM4_CMD_DEEP_POWER_DOWN_EXIT

#define MRAM4_CMD_DEEP_POWER_DOWN_EXIT 0xAB

◆ MRAM4_CMD_ERASE_32KB

#define MRAM4_CMD_ERASE_32KB 0x52

◆ MRAM4_CMD_ERASE_32KB_4BYTE_ADDRESS

#define MRAM4_CMD_ERASE_32KB_4BYTE_ADDRESS 0x5C

◆ MRAM4_CMD_ERASE_4KB

#define MRAM4_CMD_ERASE_4KB 0x20

◆ MRAM4_CMD_ERASE_4KB_4_BYTE_ADDRESS

#define MRAM4_CMD_ERASE_4KB_4_BYTE_ADDRESS 0x21

◆ MRAM4_CMD_ERASE_BULK_CHIP

#define MRAM4_CMD_ERASE_BULK_CHIP 0xC7

◆ MRAM4_CMD_ERASE_CHIP

#define MRAM4_CMD_ERASE_CHIP 0x60

◆ MRAM4_CMD_ERASE_SECTOR

#define MRAM4_CMD_ERASE_SECTOR 0xD8

◆ MRAM4_CMD_ERASE_SECTOR_4BYTE_ADDRESS

#define MRAM4_CMD_ERASE_SECTOR_4BYTE_ADDRESS 0xDC

◆ MRAM4_CMD_INTERFACE_ACTIVATION_CRC

#define MRAM4_CMD_INTERFACE_ACTIVATION_CRC 0x9B

◆ MRAM4_CMD_OTP_READ

#define MRAM4_CMD_OTP_READ 0x4B

◆ MRAM4_CMD_OTP_WRITE

#define MRAM4_CMD_OTP_WRITE 0x42

◆ MRAM4_CMD_READ

#define MRAM4_CMD_READ 0x03

◆ MRAM4_CMD_READ_4BYTE_ADDR

#define MRAM4_CMD_READ_4BYTE_ADDR 0x13

◆ MRAM4_CMD_READ_FAST_4BYTE_ADDR

#define MRAM4_CMD_READ_FAST_4BYTE_ADDR 0x0C

◆ MRAM4_CMD_READ_FAST_DTR

#define MRAM4_CMD_READ_FAST_DTR 0x0D

◆ MRAM4_CMD_READ_FAST_DTR_4BYTE_ADDR

#define MRAM4_CMD_READ_FAST_DTR_4BYTE_ADDR 0x0E

◆ MRAM4_CMD_READ_FAST_DUAL_IO

#define MRAM4_CMD_READ_FAST_DUAL_IO 0xBB

◆ MRAM4_CMD_READ_FAST_DUAL_IO_4BYTE_ADDR

#define MRAM4_CMD_READ_FAST_DUAL_IO_4BYTE_ADDR 0xBC

◆ MRAM4_CMD_READ_FAST_DUAL_IO_DTR

#define MRAM4_CMD_READ_FAST_DUAL_IO_DTR 0xBD

◆ MRAM4_CMD_READ_FAST_DUAL_IO_DTR_4BYTE_ADDR

#define MRAM4_CMD_READ_FAST_DUAL_IO_DTR_4BYTE_ADDR 0xBE

◆ MRAM4_CMD_READ_FAST_DUAL_OUTPUT

#define MRAM4_CMD_READ_FAST_DUAL_OUTPUT 0x3B

◆ MRAM4_CMD_READ_FAST_DUAL_OUTPUT_4BYTE_ADDR

#define MRAM4_CMD_READ_FAST_DUAL_OUTPUT_4BYTE_ADDR 0x3C

◆ MRAM4_CMD_READ_FAST_DUAL_OUTPUT_DTR

#define MRAM4_CMD_READ_FAST_DUAL_OUTPUT_DTR 0x3D

◆ MRAM4_CMD_READ_FAST_OCTAL_IO

#define MRAM4_CMD_READ_FAST_OCTAL_IO 0xCB

◆ MRAM4_CMD_READ_FAST_OCTAL_IO_4BYTE_ADDR

#define MRAM4_CMD_READ_FAST_OCTAL_IO_4BYTE_ADDR 0xCC

◆ MRAM4_CMD_READ_FAST_OCTAL_IO_DTR

#define MRAM4_CMD_READ_FAST_OCTAL_IO_DTR 0xFD

◆ MRAM4_CMD_READ_FAST_OCTAL_OUTPUT

#define MRAM4_CMD_READ_FAST_OCTAL_OUTPUT 0x8B

◆ MRAM4_CMD_READ_FAST_OCTAL_OUTPUT_4BYTE_ADDR

#define MRAM4_CMD_READ_FAST_OCTAL_OUTPUT_4BYTE_ADDR 0x7C

◆ MRAM4_CMD_READ_FAST_OCTAL_OUTPUT_DTR

#define MRAM4_CMD_READ_FAST_OCTAL_OUTPUT_DTR 0x9D

◆ MRAM4_CMD_READ_FAST_QUAD_IO

#define MRAM4_CMD_READ_FAST_QUAD_IO 0xEB

◆ MRAM4_CMD_READ_FAST_QUAD_IO_4BYTE_ADDR

#define MRAM4_CMD_READ_FAST_QUAD_IO_4BYTE_ADDR 0xEC

◆ MRAM4_CMD_READ_FAST_QUAD_IO_DTR

#define MRAM4_CMD_READ_FAST_QUAD_IO_DTR 0xED

◆ MRAM4_CMD_READ_FAST_QUAD_IO_DTR_4BYTE_ADDR

#define MRAM4_CMD_READ_FAST_QUAD_IO_DTR_4BYTE_ADDR 0xEE

◆ MRAM4_CMD_READ_FAST_QUAD_OUTPUT

#define MRAM4_CMD_READ_FAST_QUAD_OUTPUT 0x6B

◆ MRAM4_CMD_READ_FAST_QUAD_OUTPUT_4BYTE_ADDR

#define MRAM4_CMD_READ_FAST_QUAD_OUTPUT_4BYTE_ADDR 0x6C

◆ MRAM4_CMD_READ_FAST_QUAD_OUTPUT_DTR

#define MRAM4_CMD_READ_FAST_QUAD_OUTPUT_DTR 0x6D

◆ MRAM4_CMD_READ_FAST_XIP

#define MRAM4_CMD_READ_FAST_XIP 0x0B

◆ MRAM4_CMD_READ_FLAG_STATUS_REG

#define MRAM4_CMD_READ_FLAG_STATUS_REG 0x70

◆ MRAM4_CMD_READ_GENERAL_PURPOSE_READ_REG

#define MRAM4_CMD_READ_GENERAL_PURPOSE_READ_REG 0x96

◆ MRAM4_CMD_READ_ID

#define MRAM4_CMD_READ_ID 0x9E

◆ MRAM4_CMD_READ_ID_MIO

#define MRAM4_CMD_READ_ID_MIO 0xAF

◆ MRAM4_CMD_READ_NVOL_CFG_REG

#define MRAM4_CMD_READ_NVOL_CFG_REG 0xB5

◆ MRAM4_CMD_READ_STATUS_REG

#define MRAM4_CMD_READ_STATUS_REG 0x05

◆ MRAM4_CMD_READ_VOL_CFG_REG

#define MRAM4_CMD_READ_VOL_CFG_REG 0x85

◆ MRAM4_CMD_READ_WORD_QUAD_IO

#define MRAM4_CMD_READ_WORD_QUAD_IO 0xE7

◆ MRAM4_CMD_RESET_ENABLE

#define MRAM4_CMD_RESET_ENABLE 0x66

MRAM 4 description register.

Specified register for description of MRAM 4 Click driver.

◆ MRAM4_CMD_RESET_MEMORY

#define MRAM4_CMD_RESET_MEMORY 0x99

◆ MRAM4_CMD_TDP_READ

#define MRAM4_CMD_TDP_READ 0xF1

◆ MRAM4_CMD_TDP_READ_DTR

#define MRAM4_CMD_TDP_READ_DTR 0xF2

◆ MRAM4_CMD_TDP_WRITE

#define MRAM4_CMD_TDP_WRITE 0xF0

◆ MRAM4_CMD_WRITE_DISABLE

#define MRAM4_CMD_WRITE_DISABLE 0x04

◆ MRAM4_CMD_WRITE_ENABLE

#define MRAM4_CMD_WRITE_ENABLE 0x06

◆ MRAM4_CMD_WRITE_FAST_OCTAL_INPUT_EXT_4BYTE

#define MRAM4_CMD_WRITE_FAST_OCTAL_INPUT_EXT_4BYTE 0x8E

◆ MRAM4_CMD_WRITE_NVOL_CFG_REG

#define MRAM4_CMD_WRITE_NVOL_CFG_REG 0xB1

◆ MRAM4_CMD_WRITE_PR_4BYTE_ADDRESS

#define MRAM4_CMD_WRITE_PR_4BYTE_ADDRESS 0x12

◆ MRAM4_CMD_WRITE_PR_FAST_DUAL_INPUT

#define MRAM4_CMD_WRITE_PR_FAST_DUAL_INPUT 0xA2

◆ MRAM4_CMD_WRITE_PR_FAST_DUAL_INPUT_EXT

#define MRAM4_CMD_WRITE_PR_FAST_DUAL_INPUT_EXT 0xD2

◆ MRAM4_CMD_WRITE_PR_FAST_OCTAL_INPUT

#define MRAM4_CMD_WRITE_PR_FAST_OCTAL_INPUT 0x82

◆ MRAM4_CMD_WRITE_PR_FAST_OCTAL_INPUT_4BYTE

#define MRAM4_CMD_WRITE_PR_FAST_OCTAL_INPUT_4BYTE 0x84

◆ MRAM4_CMD_WRITE_PR_FAST_OCTAL_INPUT_EXT

#define MRAM4_CMD_WRITE_PR_FAST_OCTAL_INPUT_EXT 0xC2

◆ MRAM4_CMD_WRITE_PR_FAST_QUAD_INPUT

#define MRAM4_CMD_WRITE_PR_FAST_QUAD_INPUT 0x32

◆ MRAM4_CMD_WRITE_PR_FAST_QUAD_INPUT_4BYTE

#define MRAM4_CMD_WRITE_PR_FAST_QUAD_INPUT_4BYTE 0x34

◆ MRAM4_CMD_WRITE_PR_FAST_QUAD_INPUT_EXT

#define MRAM4_CMD_WRITE_PR_FAST_QUAD_INPUT_EXT 0x38

◆ MRAM4_CMD_WRITE_PR_FAST_QUAD_INPUT_EXT_4BYTE

#define MRAM4_CMD_WRITE_PR_FAST_QUAD_INPUT_EXT_4BYTE 0x3E

◆ MRAM4_CMD_WRITE_PR_PAGE

#define MRAM4_CMD_WRITE_PR_PAGE 0x02

◆ MRAM4_CMD_WRITE_STATUS_REG

#define MRAM4_CMD_WRITE_STATUS_REG 0x01

◆ MRAM4_CMD_WRITE_VOL_CFG_REG

#define MRAM4_CMD_WRITE_VOL_CFG_REG 0x81

Macros