nvsram2.h

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/****************************************************************************
** Copyright (C) 2020 MikroElektronika d.o.o.
** Contact: https://www.mikroe.com/contact
**
** Permission is hereby granted, free of charge, to any person obtaining a copy
** of this software and associated documentation files (the "Software"), to deal
** in the Software without restriction, including without limitation the rights
** to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
** copies of the Software, and to permit persons to whom the Software is
** furnished to do so, subject to the following conditions:
** The above copyright notice and this permission notice shall be
** included in all copies or substantial portions of the Software.
**
** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
**  USE OR OTHER DEALINGS IN THE SOFTWARE.
****************************************************************************/
 
#ifndef NVSRAM2_H
#define NVSRAM2_H
 
#ifdef __cplusplus
extern "C"{
#endif
 
#ifdef PREINIT_SUPPORTED
#include "preinit.h"
#endif
 
#ifdef MikroCCoreVersion
    #if MikroCCoreVersion >= 1
        #include "delays.h"
    #endif
#endif
 
#include "drv_digital_out.h"
#include "drv_digital_in.h"
#include "drv_spi_master.h"
 
#define NVSRAM2_STATUS_RDSR                                        0x05
#define NVSRAM2_STATUS_FRDSR                                       0x0A
#define NVSRAM2_STATUS_WRSR                                        0x01
#define NVSRAM2_STATUS_WREN                                        0x06
#define NVSRAM2_STATUS_WRDI                                        0x04
 
#define NVSRAM2_SRAM_READ                                          0x03
#define NVSRAM2_SRAM_FREAD                                         0x0B
#define NVSRAM2_SRAM_WRITE                                         0x02
 
#define NVSRAM2_SPEC_NV_STORE                                      0x3C
#define NVSRAM2_SPEC_NV_RECALL                                     0x60
#define NVSRAM2_SPEC_NV_ASENB                                      0x59
#define NVSRAM2_SPEC_NV_ASDISB                                     0x19
                                                                  
#define NVSRAM2_SPEC_SLEEP                                         0xB9
#define NVSRAM2_SPEC_WRSN                                          0xC2
#define NVSRAM2_SPEC_RDSN                                          0xC3
#define NVSRAM2_SPEC_FRDSN                                         0xC9
#define NVSRAM2_SPEC_RDID                                          0x9F
#define NVSRAM2_SPEC_FRDID                                         0x99
                                                                
#define NVSRAM2_STATUS_RDY                                         0x01
#define NVSRAM2_STATUS_WEN                                         0x02
#define NVSRAM2_STATUS_BP0                                         0x04
#define NVSRAM2_STATUS_BP1                                         0x08
#define NVSRAM2_STATUS_SNL                                         0x40
#define NVSRAM2_STATUS_WPEN                                        0x80
 
#define NVSRAM2_HOLD_ENABLE                                        0x00
#define NVSRAM2_HOLD_DISABLE                                       0x01
 
#define NVSRAM2_DUMMY_BYTE                                         0x00
 // nvsram2_set
 
#define NVSRAM2_MAP_MIKROBUS( cfg, mikrobus ) \
    cfg.miso = MIKROBUS( mikrobus, MIKROBUS_MISO ); \
    cfg.mosi = MIKROBUS( mikrobus, MIKROBUS_MOSI ); \
    cfg.sck  = MIKROBUS( mikrobus, MIKROBUS_SCK ); \
    cfg.cs   = MIKROBUS( mikrobus, MIKROBUS_CS ); \
    cfg.hld = MIKROBUS( mikrobus, MIKROBUS_PWM ); \
    
 // nvsram2_map
 // nvsram2
 
typedef struct
{
    // Output pins
    
    digital_out_t  hld;                             
    // Modules
    
    spi_master_t  spi;                              
    pin_name_t  chip_select;                        
} nvsram2_t;
 
typedef struct
{
    // Communication gpio pins
    
    pin_name_t  miso;                                    
    pin_name_t  mosi;                                    
    pin_name_t  sck;                                     
    pin_name_t  cs;                                      
    // Additional gpio pins
    
    pin_name_t  hld;                                     
    // static variable
    
    uint32_t                           spi_speed;        
    spi_master_mode_t                  spi_mode;         
    spi_master_chip_select_polarity_t  cs_polarity;      
} nvsram2_cfg_t;
 
typedef enum
{
   NVSRAM2_OK = 0,
   NVSRAM2_ERROR = -1
 
} nvsram2_return_value_t;
 
void nvsram2_cfg_setup ( nvsram2_cfg_t *cfg );
 
err_t nvsram2_init ( nvsram2_t *ctx, nvsram2_cfg_t *cfg );
 
err_t nvsram2_default_cfg ( nvsram2_t *ctx );
 
err_t nvsram2_generic_write ( nvsram2_t *ctx, uint8_t reg, uint8_t *data_in, uint8_t len );
 
err_t nvsram2_generic_read ( nvsram2_t *ctx, uint8_t reg, uint8_t *data_out, uint8_t len );
 
void nvsram2_hold ( nvsram2_t *ctx, uint8_t en_hold );
 
void nvsram2_set_cmd ( nvsram2_t *ctx, uint8_t cmd );
 
uint8_t nvsram2_read_status ( nvsram2_t *ctx );
 
uint8_t nvsram2_fast_read_status ( nvsram2_t *ctx );
 
void nvsram2_write_status ( nvsram2_t *ctx, uint8_t data_byte );
 
void nvsram2_burst_read ( nvsram2_t *ctx, uint32_t mem_addr, uint8_t *p_rx_data, uint8_t n_bytes );
 
void nvsram2_burst_write ( nvsram2_t *ctx, uint32_t mem_addr, uint8_t *p_tx_data, uint8_t n_bytes );
 
uint32_t nvsram2_read_id ( nvsram2_t *ctx );
 
#ifdef __cplusplus
}
#endif
#endif // NVSRAM2_H
 
 // nvsram2
 
// ------------------------------------------------------------------------ END