nvsram3.h

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/****************************************************************************
** Copyright (C) 2020 MikroElektronika d.o.o.
** Contact: https://www.mikroe.com/contact
**
** Permission is hereby granted, free of charge, to any person obtaining a copy
** of this software and associated documentation files (the "Software"), to deal
** in the Software without restriction, including without limitation the rights
** to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
** copies of the Software, and to permit persons to whom the Software is
** furnished to do so, subject to the following conditions:
** The above copyright notice and this permission notice shall be
** included in all copies or substantial portions of the Software.
**
** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
**  USE OR OTHER DEALINGS IN THE SOFTWARE.
****************************************************************************/
 
#ifndef NVSRAM3_H
#define NVSRAM3_H
 
#ifdef __cplusplus
extern "C"{
#endif
 
#ifdef PREINIT_SUPPORTED
#include "preinit.h"
#endif
 
#ifdef MikroCCoreVersion
    #if MikroCCoreVersion >= 1
        #include "delays.h"
    #endif
#endif
 
#include "drv_digital_out.h"
#include "drv_digital_in.h"
#include "drv_i2c_master.h"
 
#define NVSRAM3_CONTROL_REG_MEM_CTRL                 0x00
#define NVSRAM3_CONTROL_REG_SERIAL_NUMBER         0x01
#define NVSRAM3_CONTROL_REG_DEVICE_ID                 0x09
#define NVSRAM3_CONTROL_REG_CMD                          0xAA
 
#define NVSRAM3_RTC_REG_FLAGS                                    0x00
#define NVSRAM3_RTC_REG_TIME_KEEPING_CENTURIES       0x01
#define NVSRAM3_RTC_REG_ALARM_SECONDS                     0x02
#define NVSRAM3_RTC_REG_ALARM_MINUTES                     0x03
#define NVSRAM3_RTC_REG_ALARM_HOURS                        0x04
#define NVSRAM3_RTC_REG_ALARM_DAY                            0x05
#define NVSRAM3_RTC_REG_INTERRUPT_STATUS_CONTROL 0x06
#define NVSRAM3_RTC_REG_WATCHDOG_TIMER                  0x07
#define NVSRAM3_RTC_REG_CALIBRATION_CONTROL           0x08
#define NVSRAM3_RTC_REG_TIME_KEEPING_SECONDS          0x09
#define NVSRAM3_RTC_REG_TIME_KEEPING_MINUTES          0x0A
#define NVSRAM3_RTC_REG_TIME_KEEPING_HOURS             0x0B
#define NVSRAM3_RTC_REG_TIME_KEEPING_DAY                 0x0C
#define NVSRAM3_RTC_REG_TIME_KEEPING_DATE                0x0D
#define NVSRAM3_RTC_REG_TIME_KEEPING_MONTHS           0x0E
#define NVSRAM3_RTC_REG_TIME_KEEPING_YEARS              0x0F
 
 // nvsram3_reg
 
#define NVSRAM3_SERIAL_NUMBER_LOCK        0x40
#define NVSRAM3_SERIAL_NUMBER_UNLOCK    0x00
#define NVSRAM3_BLOCK_PROTECT_QUARTER 0x04
#define NVSRAM3_BLOCK_PROTECT_HALF        0x08
#define NVSRAM3_BLOCK_PROTECT_FULL        0x0C
 
#define NVSRAM3_STORE_COMMAND         0x3C
#define NVSRAM3_RECALL_COMMAND        0x60
#define NVSRAM3_ASENB_COMMAND         0x59
#define NVSRAM3_ASDISB_COMMAND        0x19
#define NVSRAM3_SLEEP_COMMAND          0xB9
 
#define NVSRAM3_RTC_WRITE_ENABLE      0x02
#define NVSRAM3_RTC_WRITE_DISABLE     0x00
#define NVSRAM3_RTC_READ_ENABLE        0x01
#define NVSRAM3_RTC_READ_DISABLE      0x00
 
#define NVSRAM3_MEMORY_DEV_ADDR_0  0x50
#define NVSRAM3_MEMORY_DEV_ADDR_1  0x52
#define NVSRAM3_MEMORY_DEV_ADDR_2  0x54
#define NVSRAM3_MEMORY_DEV_ADDR_3  0x56
 
#define NVSRAM3_RTC_DEV_ADDR_0  0x68
#define NVSRAM3_RTC_DEV_ADDR_1  0x6A
#define NVSRAM3_RTC_DEV_ADDR_2  0x6C
#define NVSRAM3_RTC_DEV_ADDR_3  0x6E
 
#define NVSRAM3_CONTROL_DEV_ADDR_0  0x18
#define NVSRAM3_CONTROL_DEV_ADDR_1  0x1A
#define NVSRAM3_CONTROL_DEV_ADDR_2  0x1C
#define NVSRAM3_CONTROL_DEV_ADDR_3  0x1E
 
#define NVSRAM3_HSB_ENABLE                                        0x00
#define NVSRAM3_HSB_DISABLE                                       0x01
 
#define NVSRAM3_WP_ENABLE                                        0x00
#define NVSRAM3_WP_DISABLE                                       0x01
 
 // nvsram3_set
 
#define NVSRAM3_SUCCESS            0
#define NVSRAM3_ERROR              -1
 
 
 // status
 
#define NVSRAM3_MAP_MIKROBUS( cfg, mikrobus ) \
    cfg.scl = MIKROBUS( mikrobus, MIKROBUS_SCL ); \
    cfg.sda = MIKROBUS( mikrobus, MIKROBUS_SDA ); \
    cfg.hsb = MIKROBUS( mikrobus, MIKROBUS_RST ); \
    cfg.wp = MIKROBUS( mikrobus, MIKROBUS_PWM ); \
    cfg.int_pin = MIKROBUS( mikrobus, MIKROBUS_INT )
 
 // nvsram3_map
 // nvsram3
 
typedef struct
{
    // Output pins
 
    digital_out_t  hsb;     
    digital_out_t  wp;     
    // Input pins
 
    digital_in_t  int_pin;      
    // Modules
 
    i2c_master_t i2c;                                
    // I2C slave address
 
    uint8_t slave_address;                           
} nvsram3_t;
 
typedef struct
{
    pin_name_t  scl;        
    pin_name_t  sda;        
    pin_name_t  hsb;       
    pin_name_t  wp;       
    pin_name_t  int_pin;       
    uint32_t  i2c_speed;                                
    uint8_t   i2c_address;                              
} nvsram3_cfg_t;
 
typedef struct 
{
    
    uint8_t hours; 
    uint8_t min;
    uint8_t sec; 
    
} nvsram3_rtc_time_t;
 
typedef struct 
{
    
    uint16_t year;
    uint8_t month;
    uint8_t day;
    uint8_t day_of_week;
} nvsram3_rtc_date_t;
 
typedef struct 
{
    
    uint8_t day;
    uint8_t hours; 
    uint8_t min;
    uint8_t sec; 
    
} nvsram3_rtc_alarm_t;
 
void nvsram3_cfg_setup ( nvsram3_cfg_t *cfg );
 
err_t nvsram3_init ( nvsram3_t *ctx, nvsram3_cfg_t *cfg );
 
err_t nvsram3_default_cfg ( nvsram3_t *ctx );
 
err_t nvsram3_generic_write ( nvsram3_t *ctx, uint8_t reg, uint8_t *tx_buf, uint8_t tx_len );
 
err_t nvsram3_generic_read ( nvsram3_t *ctx, uint8_t reg, uint8_t *rx_buf, uint8_t rx_len );
 
err_t nvsram3_send_cmd ( nvsram3_t *ctx, uint8_t cmd );
 
err_t nvsram3_memory_write ( nvsram3_t *ctx, uint32_t mem_addr, uint8_t *data_in, uint8_t n_bytes );
 
err_t nvsram3_memory_read ( nvsram3_t *ctx, uint32_t mem_addr, uint8_t *data_out, uint8_t n_bytes );
 
uint32_t nvsram3_get_device_id ( nvsram3_t *ctx );
 
err_t nvsram3_rtc_read_reg ( nvsram3_t *ctx, uint8_t rtc_reg, uint8_t *data_out );
 
err_t nvsram3_rtc_write_reg ( nvsram3_t *ctx, uint8_t rtc_reg, uint8_t data_in ) ;
 
void nvsram3_get_rtc_time ( nvsram3_t *ctx, nvsram3_rtc_time_t *rtc_time );
 
err_t nvsram3_set_rtc_time ( nvsram3_t *ctx, nvsram3_rtc_time_t rtc_time );
 
void nvsram3_get_rtc_date ( nvsram3_t *ctx, nvsram3_rtc_date_t *rtc_date );
 
err_t nvsram3_set_rtc_date ( nvsram3_t *ctx, nvsram3_rtc_date_t rtc_date );
 
void nvsram3_get_rtc_alarm ( nvsram3_t *ctx, nvsram3_rtc_alarm_t *rtc_alarm );
 
err_t nvsram3_set_rtc_alarm ( nvsram3_t *ctx, nvsram3_rtc_alarm_t rtc_alarm );
 
err_t nvsram3_hardware_store ( nvsram3_t *ctx, uint8_t state );
 
err_t nvsram3_hw_write_protection ( nvsram3_t *ctx, uint8_t state );
 
#ifdef __cplusplus
}
#endif
#endif // NVSRAM3_H
 
 // nvsram3
 
// ------------------------------------------------------------------------ END