reram2.h

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/****************************************************************************
** Copyright (C) 2020 MikroElektronika d.o.o.
** Contact: https://www.mikroe.com/contact
**
** Permission is hereby granted, free of charge, to any person obtaining a copy
** of this software and associated documentation files (the "Software"), to deal
** in the Software without restriction, including without limitation the rights
** to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
** copies of the Software, and to permit persons to whom the Software is
** furnished to do so, subject to the following conditions:
** The above copyright notice and this permission notice shall be
** included in all copies or substantial portions of the Software.
**
** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
**  USE OR OTHER DEALINGS IN THE SOFTWARE.
****************************************************************************/
 
#ifndef RERAM2_H
#define RERAM2_H
 
#ifdef __cplusplus
extern "C"{
#endif
 
#ifdef PREINIT_SUPPORTED
#include "preinit.h"
#endif
 
#ifdef MikroCCoreVersion
    #if MikroCCoreVersion >= 1
        #include "delays.h"
    #endif
#endif
 
#include "drv_digital_out.h"
#include "drv_spi_master.h"
#include "spi_specifics.h"
 
#define RERAM2_CMD_WREN              0x06
#define RERAM2_CMD_WRDI              0x04
#define RERAM2_CMD_RDSR              0x05
#define RERAM2_CMD_WRSR              0x01
#define RERAM2_CMD_READ              0x03
#define RERAM2_CMD_WRITE             0x02
#define RERAM2_CMD_RDID              0x9F
#define RERAM2_CMD_RDUID             0x83
#define RERAM2_CMD_SLEEP             0xB9
#define RERAM2_CMD_PWDN              0xE2
 
 // reram2_cmd
 
#define RERAM2_DEVICE_ID             0x047FAA03
#define RERAM2_MANUFACTURER_ID       0x04
#define RERAM2_CONTINUATION_CODE     0x7F
#define RERAM2_PRODUCT_ID            0xAA03
 
#define RERAM2_HOLD_ENABLE                                      0x00
#define RERAM2_HOLD_DISABLE                                     0x01
 
#define RERAM2_WP_ENABLE                                        0x00
#define RERAM2_WP_DISABLE                                       0x01
 
#define RERAM2_SET_DATA_SAMPLE_EDGE      SET_SPI_DATA_SAMPLE_EDGE
#define RERAM2_SET_DATA_SAMPLE_MIDDLE    SET_SPI_DATA_SAMPLE_MIDDLE
 
 // reram2_set
 
#define RERAM2_MAP_MIKROBUS( cfg, mikrobus )        \
    cfg.miso = MIKROBUS( mikrobus, MIKROBUS_MISO ); \
    cfg.mosi = MIKROBUS( mikrobus, MIKROBUS_MOSI ); \
    cfg.sck  = MIKROBUS( mikrobus, MIKROBUS_SCK );  \
    cfg.cs   = MIKROBUS( mikrobus, MIKROBUS_CS );   \
    cfg.ho = MIKROBUS( mikrobus, MIKROBUS_RST );    \
    cfg.wp = MIKROBUS( mikrobus, MIKROBUS_PWM )
 
 // reram2_map
 // reram2
 
typedef struct
{
    // Output pins
    digital_out_t  ho;         
    digital_out_t  wp;         
    // Modules
    spi_master_t  spi;         
    pin_name_t  chip_select;   
} reram2_t;
 
typedef struct
{
    // Communication gpio pins
    pin_name_t  miso;    
    pin_name_t  mosi;    
    pin_name_t  sck;     
    pin_name_t  cs;      
    // Additional gpio pins
    pin_name_t  ho;      
    pin_name_t  wp;      
    // static variable
    uint32_t                           spi_speed;        
    spi_master_mode_t                  spi_mode;         
    spi_master_chip_select_polarity_t  cs_polarity;      
} reram2_cfg_t;
 
typedef struct
{
    uint8_t  write_protect;
    uint8_t  block_protect;
    uint8_t  write_enable_latch;
    uint8_t  write_in_progress;
 
} reram2_status_t;
 
typedef struct
{
    uint8_t   manufacturer_id;
    uint8_t   continuation_code;
    uint16_t  product_id;
    uint8_t   lot_id[ 5 ];
    uint8_t   wafer_id;
    uint16_t  chip_id;
 
} reram2_dev_id_t;
 
typedef enum
{
    RERAM2_OK = 0,
    RERAM2_ERROR = -1
 
} reram2_return_value_t;
 
void reram2_cfg_setup ( reram2_cfg_t *cfg );
 
err_t reram2_init ( reram2_t *ctx, reram2_cfg_t *cfg );
 
err_t reram2_default_cfg ( reram2_t *ctx );
 
err_t reram2_generic_write ( reram2_t *ctx, uint8_t reg, uint8_t *data_in, uint8_t len );
 
err_t reram2_generic_read ( reram2_t *ctx, uint8_t reg, uint8_t *data_out, uint8_t len );
 
err_t reram2_set_hold ( reram2_t *ctx, uint8_t en_hold );
 
err_t reram2_set_write_protect ( reram2_t *ctx, uint8_t en_wp );
 
err_t reram2_wake_up ( reram2_t *ctx );
 
err_t reram2_send_command ( reram2_t *ctx, uint8_t cmd );
 
err_t reram2_get_status ( reram2_t *ctx, reram2_status_t *status );
 
err_t reram2_read_device_id ( reram2_t *ctx, reram2_dev_id_t *dev_id );
 
err_t reram2_check_device_id ( reram2_t *ctx );
 
err_t reram2_write_memory ( reram2_t *ctx, uint32_t mem_addr, uint8_t *data_in, uint16_t len );
 
err_t reram2_read_memory ( reram2_t *ctx, uint32_t mem_addr, uint8_t *data_out, uint16_t len );
 
#ifdef __cplusplus
}
#endif
#endif // RERAM2_H
 
 // reram2
 
// ------------------------------------------------------------------------ END