sram4.h

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/****************************************************************************
** Copyright (C) 2020 MikroElektronika d.o.o.
** Contact: https://www.mikroe.com/contact
**
** Permission is hereby granted, free of charge, to any person obtaining a copy
** of this software and associated documentation files (the "Software"), to deal
** in the Software without restriction, including without limitation the rights
** to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
** copies of the Software, and to permit persons to whom the Software is
** furnished to do so, subject to the following conditions:
** The above copyright notice and this permission notice shall be
** included in all copies or substantial portions of the Software.
**
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** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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#ifndef SRAM4_H
#define SRAM4_H
 
#ifdef __cplusplus
extern "C"{
#endif
 
#ifdef PREINIT_SUPPORTED
#include "preinit.h"
#endif
 
#ifdef MikroCCoreVersion
    #if MikroCCoreVersion >= 1
        #include "delays.h"
    #endif
#endif
 
#include "drv_digital_out.h"
#include "drv_digital_in.h"
#include "drv_spi_master.h"
#include "spi_specifics.h"
 
#define SRAM4_REG_RDSR          0x05/*< Read status register*/
#define SRAM4_REG_FAST_RDSR     0x09/*< Fast Read status register*/
#define SRAM4_REG_WRSR          0x01/*< Write status register*/
#define SRAM4_REG_WREN          0x06/*< Set write enable latch*/
#define SRAM4_REG_WRDI          0x04/*< Reset write enable latch*/
#define SRAM4_REG_READ          0x03/*< Read data from memory array*/
#define SRAM4_REG_FAST_READ     0x0B/*< Fast read data*/
#define SRAM4_REG_WRITE         0x02/*< Write data to memory array*/
#define SRAM4_REG_STORE         0x3C/*< Software STORE*/
#define SRAM4_REG_RECALL        0x60/*< Software RECALL*/
#define SRAM4_REG_ASENB         0x59/*< AutoStore Enable*/
#define SRAM4_REG_ASDISB        0x19/*< AutoStore Disable*/
#define SRAM4_REG_SLEEP         0xB9/*< Sleep mode enable*/
#define SRAM4_REG_WRSN          0xC2/*< Write serial number*/
#define SRAM4_REG_RDSN          0xC3/*< Read serial number*/
#define SRAM4_REG_FAST_RDSN     0xC9/*< Fast serial number read*/
#define SRAM4_REG_RDID          0x9F/*< Read ID's*/
#define SRAM4_REG_FAST_RDID     0x9E/*< Fast read ID's*/
 
 // sram4_reg
 
#define SRAM4_DEVICE_ID 0x06818818
 
#define SRAM4_SET_DATA_SAMPLE_EDGE      SET_SPI_DATA_SAMPLE_EDGE
#define SRAM4_SET_DATA_SAMPLE_MIDDLE    SET_SPI_DATA_SAMPLE_MIDDLE
 
 // sram4_set
 
#define SRAM4_MAP_MIKROBUS( cfg, mikrobus ) \
    cfg.miso = MIKROBUS( mikrobus, MIKROBUS_MISO ); \
    cfg.mosi = MIKROBUS( mikrobus, MIKROBUS_MOSI ); \
    cfg.sck  = MIKROBUS( mikrobus, MIKROBUS_SCK ); \
    cfg.cs   = MIKROBUS( mikrobus, MIKROBUS_CS ); \
    cfg.hold = MIKROBUS( mikrobus, MIKROBUS_PWM );
 
 // sram4_map
 // sram4
 
typedef struct
{
    // Output pins
    digital_out_t  hold;        
    // Modules
    spi_master_t  spi;          
    pin_name_t  chip_select;    
    uint32_t device_id;         
} sram4_t;
 
typedef struct
{
    // Communication gpio pins
    pin_name_t  miso;   
    pin_name_t  mosi;   
    pin_name_t  sck;    
    pin_name_t  cs;     
    // Additional gpio pins
    pin_name_t  hold;   
    // static variable
    uint32_t                           spi_speed;   
    spi_master_mode_t                  spi_mode;    
    spi_master_chip_select_polarity_t  cs_polarity; 
} sram4_cfg_t;
 
typedef enum
{
   SRAM4_OK = 0,
   SRAM4_ERROR = -1
 
} sram4_return_value_t;
 
void sram4_cfg_setup ( sram4_cfg_t *cfg );
 
err_t sram4_init ( sram4_t *ctx, sram4_cfg_t *cfg );
 
err_t sram4_default_cfg ( sram4_t *ctx );
 
err_t sram4_generic_command ( sram4_t *ctx, uint8_t cmd );
 
err_t sram4_generic_write ( sram4_t *ctx, uint8_t reg, uint8_t *data_in, uint8_t len );
 
err_t sram4_generic_read ( sram4_t *ctx, uint8_t reg, uint8_t *data_out, uint8_t len );
 
err_t sram4_generic_write_then_read ( sram4_t *ctx, uint8_t *data_in, uint8_t in_len, uint8_t *data_out, uint8_t out_len );
 
err_t sram4_memory_write ( sram4_t *ctx, uint16_t memory_adr, uint8_t *write_data, uint8_t write_len );
 
err_t sram4_memory_read ( sram4_t *ctx, uint16_t memory_adr, uint8_t *read_data, uint8_t read_len );
 
void sram4_set_hold ( sram4_t *ctx, uint8_t state );
 
#ifdef __cplusplus
}
#endif
#endif // SRAM4_H
 
 // sram4
 
// ------------------------------------------------------------------------ END