tdc.h

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/****************************************************************************
** Copyright (C) 2020 MikroElektronika d.o.o.
** Contact: https://www.mikroe.com/contact
**
** Permission is hereby granted, free of charge, to any person obtaining a copy
** of this software and associated documentation files (the "Software"), to deal
** in the Software without restriction, including without limitation the rights
** to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
** copies of the Software, and to permit persons to whom the Software is
** furnished to do so, subject to the following conditions:
** The above copyright notice and this permission notice shall be
** included in all copies or substantial portions of the Software.
**
** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
**  USE OR OTHER DEALINGS IN THE SOFTWARE.
****************************************************************************/
 
#ifndef TDC_H
#define TDC_H
 
#ifdef __cplusplus
extern "C"{
#endif
 
#ifdef PREINIT_SUPPORTED
#include "preinit.h"
#endif
 
#ifdef MikroCCoreVersion
    #if MikroCCoreVersion >= 1
        #include "delays.h"
    #endif
#endif
 
#include "drv_digital_out.h"
#include "drv_digital_in.h"
#include "drv_spi_master.h"
 
#define TDC_REG_ADR_CONFIG1                                                0x00
#define TDC_REG_ADR_CONFIG2                                                0x01
#define TDC_REG_ADR_INT_STATUS                                             0x02
#define TDC_REG_ADR_INT_MASK                                               0x03
#define TDC_REG_ADR_COARSE_CNTR_OVF_H                                      0x04
#define TDC_REG_ADR_COARSE_CNTR_OVF_L                                      0x05
#define TDC_REG_ADR_CLOCK_CNTR_OVF_H                                       0x06
#define TDC_REG_ADR_CLOCK_CNTR_OVF_L                                       0x07
#define TDC_REG_ADR_CLOCK_CNTR_STOP_MASK_H                                 0x08
#define TDC_REG_ADR_CLOCK_CNTR_STOP_MASK_L                                 0x09
#define TDC_REG_ADR_TIME1                                                  0x10
#define TDC_REG_ADR_CLOCK_COUNT1                                           0x11
#define TDC_REG_ADR_TIME2                                                  0x12
#define TDC_REG_ADR_CLOCK_COUNT2                                           0x13
#define TDC_REG_ADR_TIME3                                                  0x14
#define TDC_REG_ADR_CLOCK_COUNT3                                           0x15
#define TDC_REG_ADR_TIME4                                                  0x16
#define TDC_REG_ADR_CLOCK_COUNT4                                           0x17
#define TDC_REG_ADR_TIME5                                                  0x18
#define TDC_REG_ADR_CLOCK_COUNT5                                           0x19
#define TDC_REG_ADR_CLOCK_COUNTX(num)                                      (TDC_REG_ADR_CLOCK_COUNT1+2*((num)-1))
#define TDC_REG_ADR_TIME6                                                  0x1A
#define TDC_REG_ADR_TIMEX(num)                                             (TDC_REG_ADR_TIME1+2*((num)-1))
#define TDC_REG_ADR_CALIBRATION1                                           0x1B
#define TDC_REG_ADR_CALIBRATION2                                           0x1C
#define TDC_REG_DEFAULTS_CONFIG2                                           0x40      
#define TDC_REG_DEFAULTS_INT_MASK                                          0x07     
 
#define TDC_REG_SHIFT_CONFIG1_FORCE_CAL                                    7
#define TDC_REG_SHIFT_CONFIG1_PARITY_EN                                    6
#define TDC_REG_SHIFT_CONFIG1_TRIGG_EDGE                                   5
#define TDC_REG_SHIFT_CONFIG1_STOP_EDGE                                    4
#define TDC_REG_SHIFT_CONFIG1_START_EDGE                                   3
#define TDC_REG_SHIFT_CONFIG1_MEAS_MODE                                    1
#define TDC_REG_SHIFT_CONFIG1_START_MEAS                                   0
 
#define TDC_REG_VAL_CONFIG1_MEAS_MODE_MIN                                  1
#define TDC_REG_VAL_CONFIG1_MEAS_MODE_MAX                                  2
#define TDC_REG_VAL_CONFIG1_MEAS_MODE(num)                                 ((num)-1)
 
 
#define TDC_REG_SHIFT_CONFIG2_CALIBRATION2_PERIODS                         6
#define TDC_REG_SHIFT_CONFIG2_AVG_CYCLES                                   3
#define TDC_REG_SHIFT_CONFIG2_NUM_STOP                                     0
 
#define TDC_REG_VAL_CONFIG2_CALIBRATION2_PERIODS_2                         0
#define TDC_REG_VAL_CONFIG2_CALIBRATION2_PERIODS_10                        1
#define TDC_REG_VAL_CONFIG2_CALIBRATION2_PERIODS_20                        2
#define TDC_REG_VAL_CONFIG2_CALIBRATION2_PERIODS_40                        3
 
#define TDC_REG_VAL_CONFIG2_AVG_CYCLES_MIN_VAL                             0
#define TDC_REG_VAL_CONFIG2_AVG_CYCLES_MIN                                 1 << TDC_REG_VAL_CONFIG2_AVG_CYCLES_MIN_VAL
#define TDC_REG_VAL_CONFIG2_AVG_CYCLES_MAX_VAL                             7
#define TDC_REG_VAL_CONFIG2_AVG_CYCLES_MAX                                 1 << TDC_REG_VAL_CONFIG2_AVG_CYCLES_MAX_VAL
 
#define TDC_REG_VAL_CONFIG2_NUM_STOP(num)                                  ((num)-1)
#define TDC_REG_VAL_CONFIG2_NUM_STOP_MAX                                   5
 
#define TDC_REG_SHIFT_INT_STATUS_MEAS_COMPLETE_FLAG                        4
#define TDC_REG_SHIFT_INT_STATUS_MEAS_STARTED_FLAG                         3
#define TDC_REG_SHIFT_INT_STATUS_CLOCK_CNTR_OVF_INT                        2
#define TDC_REG_SHIFT_INT_STATUS_COARSE_CNTR_OVF_INT                       1
#define TDC_REG_SHIFT_INT_STATUS_NEW_MEAS_INT                              0
 
#define TDC_REG_SHIFT_INT_MASK_CLOCK_CNTR_OVF_MASK                         2
#define TDC_REG_SHIFT_INT_MASK_COARSE_CNTR_OVF_MASK                        1
#define TDC_REG_SHIFT_INT_MASK_NEW_MEAS_MASK                               0
 
 // tdc_reg
 
#define TDC_CLOCK_FREQ_HZ                                                  8000000    
#define TDC_RING_OSC_FREQ_KHZ                                              8000
#define TDC_RING_OSC_FREQ_MHZ                                              TDC_RING_OSC_FREQ_KHZ/1000
#define PS_PER_K_SEC                                                       1000000000
#define US_PER_K_SEC                                                       1000000
#define PS_PER_PIC32_SEC                                                   878000
#define PS_PER_PIC_SEC                                                     160000
#define TDC_CLOCK_FREQ_HZ_PS_PER_PIC_SEC                                   0.05
#define TDC_CLOCK_FREQ_HZ_PS_PER_ARM_SEC                                   14.745
    
#define TDC_MCU_CLOCK_MODE_168_MHZ                                         0
#define TDC_MCU_CLOCK_MODE_80_MHZ                                          1
#define TDC_MCU_CLOCK_MODE_64_MHZ                                          2
 
 // tdc_set
 
#define TDC_MAP_MIKROBUS( cfg, mikrobus ) \
    cfg.miso = MIKROBUS( mikrobus, MIKROBUS_MISO ); \
    cfg.mosi = MIKROBUS( mikrobus, MIKROBUS_MOSI ); \
    cfg.sck  = MIKROBUS( mikrobus, MIKROBUS_SCK );  \
    cfg.oen = MIKROBUS( mikrobus, MIKROBUS_AN );   \
    cfg.cs   = MIKROBUS( mikrobus, MIKROBUS_CS );   \
    cfg.en = MIKROBUS( mikrobus, MIKROBUS_RST );    \
    cfg.trg = MIKROBUS( mikrobus, MIKROBUS_PWM );   \
    cfg.stop = MIKROBUS( mikrobus, MIKROBUS_CS );   \
    cfg.start = MIKROBUS( mikrobus, MIKROBUS_RST );   \
    cfg.int_pin = MIKROBUS( mikrobus, MIKROBUS_INT )
 
 // tdc_map
 // tdc
 
typedef struct
{
    // Output pins
    digital_out_t  oen;         
    digital_out_t  en;          
    digital_out_t  stop;        
    digital_out_t  start;       
    // Input pins               
    digital_in_t  trg;          
    digital_in_t  int_pin;      
    // Modules                  
    spi_master_t  spi;          
    pin_name_t  chip_select;    
} tdc_t;
 
typedef struct
{
    // Communication gpio pins
    pin_name_t  miso;       
    pin_name_t  mosi;       
    pin_name_t  sck;        
    pin_name_t  cs;         
    // Additional gpio pins
    pin_name_t  oen;       
    pin_name_t  en;        
    pin_name_t  trg;       
    pin_name_t  stop;      
    pin_name_t  start;     
    pin_name_t  int_pin;   
    // static variable
    uint32_t                           spi_speed;        
    spi_master_mode_t                  spi_mode;         
    spi_master_chip_select_polarity_t  cs_polarity;      
} tdc_cfg_t;
 
typedef enum
{
   TDC_OK = 0,
   TDC_ERROR = -1
 
} tdc_return_value_t;
 
void tdc_cfg_setup ( tdc_cfg_t *cfg );
 
err_t tdc_init ( tdc_t *ctx, tdc_cfg_t *cfg );
 
err_t tdc_default_cfg ( tdc_t *ctx );
 
err_t tdc_generic_write ( tdc_t *ctx, uint8_t reg, uint8_t *data_in, uint8_t len );
 
err_t tdc_generic_read ( tdc_t *ctx, uint8_t reg, uint8_t *data_out, uint8_t len );
 
err_t tdc_generic_write_byte ( tdc_t *ctx, uint8_t reg, uint8_t data_in );
 
err_t tdc_generic_read_byte ( tdc_t *ctx, uint8_t reg, uint8_t *data_out );
 
void tdc_gen_pulse ( tdc_t *ctx, uint32_t u_sec, uint8_t n_stops );
 
void tdc_start_measurement ( tdc_t *ctx );
 
void tdc_setup_overflow ( tdc_t *ctx, uint32_t overflow_ps );
 
err_t tdc_setup_measurement ( tdc_t *ctx, uint8_t cal_periods, uint8_t avg_cycles, uint8_t num_stops, uint8_t mode );
 
err_t tdc_get_measurement ( tdc_t *ctx, uint8_t clock_mode, uint8_t measure_num_stop, uint32_t *time, uint32_t *clock_countn, uint32_t *tof );
 
uint8_t tdc_get_interrupt ( tdc_t *ctx );
 
uint8_t tdc_get_trg ( tdc_t *ctx );
 
#ifdef __cplusplus
}
#endif
#endif // TDC_H
 
 // tdc
 
// ------------------------------------------------------------------------ END