vreg.h

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/*
 * MikroSDK - MikroE Software Development Kit
 * Copyright© 2020 MikroElektronika d.o.o.
 * 
 * Permission is hereby granted, free of charge, to any person 
 * obtaining a copy of this software and associated documentation 
 * files (the "Software"), to deal in the Software without restriction, 
 * including without limitation the rights to use, copy, modify, merge, 
 * publish, distribute, sublicense, and/or sell copies of the Software, 
 * and to permit persons to whom the Software is furnished to do so, 
 * subject to the following conditions:
 * 
 * The above copyright notice and this permission notice shall be 
 * included in all copies or substantial portions of the Software.
 * 
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 
 * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
 * OR OTHER DEALINGS IN THE SOFTWARE. 
 */
 
// ----------------------------------------------------------------------------
 
#ifndef VREG_H
#define VREG_H
 
#ifdef PREINIT_SUPPORTED
#include "preinit.h"
#endif
 
#ifdef MikroCCoreVersion
    #if MikroCCoreVersion >= 1
        #include "delays.h"
    #endif
#endif
 
#include "drv_digital_out.h"
#include "drv_digital_in.h"
#include "drv_spi_master.h"
 
 
// -------------------------------------------------------------- PUBLIC MACROS 
#define VREG_MAP_MIKROBUS( cfg, mikrobus ) \
   cfg.miso  = MIKROBUS( mikrobus, MIKROBUS_MISO ); \
   cfg.mosi  = MIKROBUS( mikrobus, MIKROBUS_MOSI ); \
   cfg.sck   = MIKROBUS( mikrobus, MIKROBUS_SCK ); \
   cfg.cs    = MIKROBUS( mikrobus, MIKROBUS_CS ); \
   cfg.cs2 = MIKROBUS( mikrobus, MIKROBUS_AN ); \
   cfg.sw = MIKROBUS( mikrobus, MIKROBUS_PWM ); 
#define VREG_RETVAL  uint8_t
 
#define VREG_OK           0x00
#define VREG_INIT_ERROR   0xFF
#define VREG_CHANNEL_0                                             0x00
#define VREG_CHANNEL_1                                             0x01
#define VREG_CHANNEL_2                                             0x02
#define VREG_CHANNEL_3                                             0x03
#define VREG_SINGLE_DIFFERENTIAL                                   0x00
#define VREG_SINGLE_ENDED                                          0x02
#define VREG_START_BIT                                             0x04
 
 // End group macro 
// --------------------------------------------------------------- PUBLIC TYPES
typedef struct
{
    // Output pins 
 
    digital_out_t cs;
    digital_out_t cs2;
    digital_out_t sw;
    
    // Modules 
 
    spi_master_t spi;
    pin_name_t chip_select;
 
} vreg_t;
 
typedef struct
{
    // Communication gpio pins 
 
    pin_name_t miso;
    pin_name_t mosi;
    pin_name_t sck;
    pin_name_t cs;
 
    // Additional gpio pins 
 
    pin_name_t cs2;
    pin_name_t sw;
 
    // static variable 
 
    uint32_t spi_speed;
    spi_master_mode_t   spi_mode;
    spi_master_chip_select_polarity_t cs_polarity;
 
} vreg_cfg_t;
 
 // End types group
 
// ----------------------------------------------- PUBLIC FUNCTION DECLARATIONS
 
#ifdef __cplusplus
extern "C"{
#endif
 
void vreg_cfg_setup ( vreg_cfg_t *cfg );
 
VREG_RETVAL vreg_init ( vreg_t *ctx, vreg_cfg_t *cfg );
 
void vreg_generic_transfer 
( 
    vreg_t *ctx, 
    uint8_t *wr_buf, 
    uint16_t wr_len, 
    uint8_t *rd_buf, 
    uint16_t rd_len 
);
 
uint16_t vreg_get_adc ( vreg_t *ctx, uint8_t channel );
 
void vreg_set_out_voltage ( vreg_t *ctx, uint16_t value_dac );
 
void vreg_set_output_voltage_procentage ( vreg_t *ctx, uint8_t value_dac_pct );
 
void vreg_start_measuring ( vreg_t *ctx );
 
void vreg_stop_measuring ( vreg_t *ctx );
 
#ifdef __cplusplus
}
#endif
#endif  // _VREG_H_
 
 // End public_function group
 
// ------------------------------------------------------------------------- END