|
#define | ACCEL14_MAP_MIKROBUS(cfg, mikrobus) |
|
#define | ACCEL14_RETVAL uint8_t |
|
#define | ACCEL14_OK 0x00 |
|
#define | ACCEL14_INIT_ERROR 0xFF |
|
#define | ACCEL14_REG_PIN_CTRL 0x02 |
|
#define | ACCEL14_REG_FIFO_CTRL1 0x07 |
|
#define | ACCEL14_REG_FIFO_CTRL2 0x08 |
|
#define | ACCEL14_REG_FIFO_CTRL3 0x09 |
|
#define | ACCEL14_REG_FIFO_CTRL4 0x0A |
|
#define | ACCEL14_REG_COUNTER_BDR_REG1 0x0B |
|
#define | ACCEL14_REG_COUNTER_BDR_REG2 0x0C |
|
#define | ACCEL14_REG_INT1_CTRL 0x0D |
|
#define | ACCEL14_REG_INT2_CTRL 0x0E |
|
#define | ACCEL14_REG_WHO_AM_I 0x0F |
|
#define | ACCEL14_REG_CTRL1_XL 0x10 |
|
#define | ACCEL14_REG_CTRL3_C 0x12 |
|
#define | ACCEL14_REG_CTRL4_C 0x13 |
|
#define | ACCEL14_REG_CTRL5_C 0x14 |
|
#define | ACCEL14_REG_CTRL6_C 0x15 |
|
#define | ACCEL14_REG_CTRL7_C 0x16 |
|
#define | ACCEL14_REG_CTRL8_XL 0x17 |
|
#define | ACCEL14_REG_CTRL10_C 0x19 |
|
#define | ACCEL14_REG_ALL_INT_SRC 0x1A |
|
#define | ACCEL14_REG_WAKE_UP_SRC 0x1B |
|
#define | ACCEL14_REG_STATUS_REG 0x1E |
|
#define | ACCEL14_REG_OUT_TEMP_L 0x20 |
|
#define | ACCEL14_REG_OUT_TEMP_H 0x21 |
|
#define | ACCEL14_REG_OUTX_L_A 0x28 |
|
#define | ACCEL14_REG_OUTX_H_A 0x29 |
|
#define | ACCEL14_REG_OUTY_L_A 0x2A |
|
#define | ACCEL14_REG_OUTY_H_A 0x2B |
|
#define | ACCEL14_REG_OUTZ_L_A 0x2C |
|
#define | ACCEL14_REG_OUTZ_H_A 0x2D |
|
#define | ACCEL14_REG_FIFO_STATUS1 0x3A |
|
#define | ACCEL14_REG_FIFO_STATUS2 0x3B |
|
#define | ACCEL14_REG_TIMESTAMP0 0x40 |
|
#define | ACCEL14_REG_TIMESTAMP1 0x41 |
|
#define | ACCEL14_REG_TIMESTAMP2 0x42 |
|
#define | ACCEL14_REG_TIMESTAMP3 0x43 |
|
#define | ACCEL14_REG_SLOPE_EN 0x56 |
|
#define | ACCEL14_REG_INTERRUPTS_EN 0x58 |
|
#define | ACCEL14_REG_WAKE_UP_THS 0x5B |
|
#define | ACCEL14_REG_WAKE_UP_DUR 0x5C |
|
#define | ACCEL14_REG_MD1_CFG 0x5E |
|
#define | ACCEL14_REG_MD2_CFG 0x5F |
|
#define | ACCEL14_REG_INTERNAL_FREQ_FINE 0x63 |
|
#define | ACCEL14_REG_X_OFS_USR 0x73 |
|
#define | ACCEL14_REG_Y_OFS_USR 0x74 |
|
#define | ACCEL14_REG_Z_OFS_USR 0x75 |
|
#define | ACCEL14_REG_FIFO_DATA_OUT_TAG 0x78 |
|
#define | ACCEL14_REG_FIFO_DATA_OUT_X_L 0x79 |
|
#define | ACCEL14_REG_FIFO_DATA_OUT_X_H 0x7A |
|
#define | ACCEL14_REG_FIFO_DATA_OUT_Y_L 0x7B |
|
#define | ACCEL14_REG_FIFO_DATA_OUT_Y_H 0x7C |
|
#define | ACCEL14_REG_FIFO_DATA_OUT_Z_L 0x7D |
|
#define | ACCEL14_REG_FIFO_DATA_OUT_Z_H 0x7E |
|
#define | ACCEL14_ID_VALUE 0x7B |
|
#define | ACCEL14_CTRL1_XL_POWER_BIT_MASK 0xE0 |
|
#define | ACCEL14_CTRL1_XL_POWER_DOWN 0x00 |
|
#define | ACCEL14_CTRL1_XL_POWER_UP 0xA0 |
|
#define | ACCEL14_CTRL1_XL_HIGH_RES_BIT_MASK 0x02 |
|
#define | ACCEL14_CTRL1_XL_HIGH_RES_FS 0x00 |
|
#define | ACCEL14_CTRL1_XL_HIGH_RES_SS 0x02 |
|
#define | ACCEL14_CTRL1_XL_GSEL_BIT_MASK 0x0C |
|
#define | ACCEL14_CTRL1_XL_GSEL_2G 0x00 |
|
#define | ACCEL14_CTRL1_XL_GSEL_16G 0x04 |
|
#define | ACCEL14_CTRL1_XL_GSEL_4G 0x08 |
|
#define | ACCEL14_CTRL1_XL_GSEL_8G 0x0C |
|
#define | ACCEL14_COEF_RES_2G 0.061 |
|
#define | ACCEL14_COEF_RES_4G 0.122 |
|
#define | ACCEL14_COEF_RES_8G 0.244 |
|
#define | ACCEL14_COEF_RES_16G 0.488 |
|
#define | ACCEL14_CTRL3_C_BOOT_NORMAL 0x00 |
|
#define | ACCEL14_CTRL3_C_BOOT_REBOOT 0x80 |
|
#define | ACCEL14_CTRL3_C_BDU_CONTINUOUS 0x00 |
|
#define | ACCEL14_CTRL3_C_BDU_READ_UPDATE 0x40 |
|
#define | ACCEL14_CTRL3_C_INT_ACTIVE_HIGH 0x00 |
|
#define | ACCEL14_CTRL3_C_INT_ACTIVE_LOW 0x20 |
|
#define | ACCEL14_CTRL3_C_PP_OD_PUSH_PULL 0x00 |
|
#define | ACCEL14_CTRL3_C_PP_OD_OPEN_DRAIN 0x10 |
|
#define | ACCEL14_CTRL3_C_SIM_SPI_4_WIRE 0x00 |
|
#define | ACCEL14_CTRL3_C_SIM_SPI_3_WIRE 0x08 |
|
#define | ACCEL14_CTRL3_C_IF_INC_DISABLE 0x00 |
|
#define | ACCEL14_CTRL3_C_IF_INC_ENABLE 0x04 |
|
#define | ACCEL14_CTRL3_C_SW_RESET_DIS 0x00 |
|
#define | ACCEL14_CTRL3_C_SW_RESET_EN 0x01 |
|
#define | ACCEL14_CTRL4_C_INT1_2_DIV 0x00 |
|
#define | ACCEL14_CTRL4_C_INT1_2_LOGIC_INT1 0x20 |
|
#define | ACCEL14_CTRL4_C_DRDY_MASK_DIS 0x00 |
|
#define | ACCEL14_CTRL4_C_DRDY_MASK_EN 0x10 |
|
#define | ACCEL14_CTRL4_C_SPI_I2C_EN 0x00 |
|
#define | ACCEL14_CTRL4_C_I2C_DISABLE 0x04 |
|
#define | ACCEL14_CTRL4_C_3REGOUT_EN 0x00 |
|
#define | ACCEL14_CTRL4_C_1AX_EN 0x01 |
|
#define | ACCEL14_CTRL5_C_ROUNDING_NO 0x00 |
|
#define | ACCEL14_CTRL5_C_ROUNDING_EN 0x20 |
|
#define | ACCEL14_CTRL5_C_ST_NORMAL 0x00 |
|
#define | ACCEL14_CTRL5_C_ST_POSITIVE 0x01 |
|
#define | ACCEL14_CTRL5_C_ST_NEGATIVE 0x02 |
|
#define | ACCEL14_CTRL6_C_USR_OFF_W_10 0x00 |
|
#define | ACCEL14_CTRL6_C_USR_OFF_W_2 0x08 |
|
#define | ACCEL14_CTRL6_C_SEL_3_AXES 0x00 |
|
#define | ACCEL14_CTRL6_C_SEL_X_AXES 0x01 |
|
#define | ACCEL14_CTRL6_C_SEL_Y_AXES 0x02 |
|
#define | ACCEL14_CTRL6_C_SEL_Z_AXES 0x03 |
|
#define | ACCEL14_CTRL7_C_USR_OFF_OUT 0x00 |
|
#define | ACCEL14_CTRL7_C_USR_ON_OUT 0x02 |
|
#define | ACCEL14_CTRL8_ODR_4 0x00 |
|
#define | ACCEL14_CTRL8_ODR_10 0x20 |
|
#define | ACCEL14_CTRL8_ODR_20 0x40 |
|
#define | ACCEL14_CTRL8_ODR_45 0x60 |
|
#define | ACCEL14_CTRL8_ODR_100 0x80 |
|
#define | ACCEL14_CTRL8_ODR_200 0xA0 |
|
#define | ACCEL14_CTRL8_ODR_400 0xC0 |
|
#define | ACCEL14_CTRL8_ODR_800 0xE0 |
|
#define | ACCEL14_CTRL8_HIGH_PASS_DIS 0x00 |
|
#define | ACCEL14_CTRL8_HIGH_PASS_EN 0x10 |
|
#define | ACCEL14_CTRL8_LPF2_HPF_DIS 0x00 |
|
#define | ACCEL14_CTRL8_LPF2_HPF_EN 0x08 |
|
#define | ACCEL14_CTRL10_TIMESTAMP_DIS 0x00 |
|
#define | ACCEL14_CTRL10_TIMESTAMP_EN 0x20 |
|
#define | ACCEL14_CHECK_ID_ERROR 0x00 |
|
#define | ACCEL14_CHECK_ID_SUCCESS 0x01 |
|
#define | ACCEL14_STATUS_DATA_READY 0x05 |
|
#define | ACCEL14_STATUS_TEMP_READY 0x04 |
|
#define | ACCEL14_STATUS_ACCEL_READY 0x01 |
|
#define | ACCEL14_NEW_DATA_NO_DATA 0x00 |
|
#define | ACCEL14_NEW_DATA_AVAILABLE 0x01 |
|
#define | ACCEL14_SPI_WRITE 0x00 |
|
#define | ACCEL14_SPI_READ 0x80 |
|
#define | ACCEL14_DUMMY 0x00 |
|