accel24.h

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/****************************************************************************
** Copyright (C) 2020 MikroElektronika d.o.o.
** Contact: https://www.mikroe.com/contact
**
** Permission is hereby granted, free of charge, to any person obtaining a copy
** of this software and associated documentation files (the "Software"), to deal
** in the Software without restriction, including without limitation the rights
** to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
** copies of the Software, and to permit persons to whom the Software is
** furnished to do so, subject to the following conditions:
** The above copyright notice and this permission notice shall be
** included in all copies or substantial portions of the Software.
**
** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
**  USE OR OTHER DEALINGS IN THE SOFTWARE.
****************************************************************************/
 
#ifndef ACCEL24_H
#define ACCEL24_H
 
#ifdef __cplusplus
extern "C"{
#endif
 
#ifdef PREINIT_SUPPORTED
#include "preinit.h"
#endif
 
#ifdef MikroCCoreVersion
    #if MikroCCoreVersion >= 1
        #include "delays.h"
    #endif
#endif
 
#include "drv_digital_out.h"
#include "drv_digital_in.h"
#include "drv_i2c_master.h"
 
#define ACCEL24_REG_INT_SRC0            0x00
#define ACCEL24_REG_INT_CLR0            0x00
#define ACCEL24_REG_INT_SRC1            0x01
#define ACCEL24_REG_INT_CLR1            0x01
#define ACCEL24_REG_STATUS              0x02
#define ACCEL24_REG_XOUT_MSB            0x03
#define ACCEL24_REG_XOUT_LSB            0x04
#define ACCEL24_REG_YOUT_MSB            0x05
#define ACCEL24_REG_YOUT_LSB            0x06
#define ACCEL24_REG_ZOUT_MSB            0x07
#define ACCEL24_REG_ZOUT_LSB            0x08
#define ACCEL24_REG_TOUT                0x09
#define ACCEL24_REG_INT_MASK0           0x0A
#define ACCEL24_REG_INT_MASK1           0x0B
#define ACCEL24_REG_DETECTION           0x0C
#define ACCEL24_REG_CONTROL             0x0D
#define ACCEL24_REG_WHO_AM_I            0x0F
 
 // accel24_reg
 
#define ACCEL24_INT_SRC0_CHORZ          0x80
#define ACCEL24_INT_SRC0_CHORXY         0x40
#define ACCEL24_INT_SRC0_SHYM           0x08
#define ACCEL24_INT_SRC0_SHYP           0x04
#define ACCEL24_INT_SRC0_SHXM           0x02
#define ACCEL24_INT_SRC0_SHXP           0x01
 
#define ACCEL24_INT_CLR0_ORZC           0x80
#define ACCEL24_INT_CLR0_ORXYC          0x40
#define ACCEL24_INT_CLR0_SHYMC          0x08
#define ACCEL24_INT_CLR0_SHYPC          0x04
#define ACCEL24_INT_CLR0_SHXMC          0x02
#define ACCEL24_INT_CLR0_SHXPC          0x01
#define ACCEL24_INT_CLR0_ALL            0xCF
 
#define ACCEL24_INT_SRC1_TILT           0x80
#define ACCEL24_INT_SRC1_ORZ            0x40
#define ACCEL24_INT_SRC1_ORXY_X_PLUS    0x00
#define ACCEL24_INT_SRC1_ORXY_Y_PLUS    0x10
#define ACCEL24_INT_SRC1_ORXY_X_MINUS   0x20
#define ACCEL24_INT_SRC1_ORXY_Y_MINUS   0x30
#define ACCEL24_INT_SRC1_ORXY_MASK      0x30
#define ACCEL24_INT_SRC1_DRDY           0x01
 
#define ACCEL24_INT_CLR1_SW_RST         0x10
#define ACCEL24_INT_CLR1_DRDYC          0x01
 
#define ACCEL24_STATUS_ORD              0x10
#define ACCEL24_STATUS_ORIZ_MSB         0x08
#define ACCEL24_STATUS_ORIZ_LSB         0x04
#define ACCEL24_STATUS_ORIXY_MSB        0x02
#define ACCEL24_STATUS_ORIXY_LSB        0x01
 
#define ACCEL24_INT_MASK0_ORZE          0x80
#define ACCEL24_INT_MASK0_ORXYE         0x40
#define ACCEL24_INT_MASK0_SHYME         0x08
#define ACCEL24_INT_MASK0_SHYPE         0x04
#define ACCEL24_INT_MASK0_SHXME         0x02
#define ACCEL24_INT_MASK0_SHXPE         0x01
#define ACCEL24_INT_MASK0_NONE          0x00
#define ACCEL24_INT_MASK0_ALL           0xCF
 
#define ACCEL24_INT_MASK1_TC            0x80
#define ACCEL24_INT_MASK1_DRDYE         0x01
 
#define ACCEL24_DETECTION_SHM           0x80
#define ACCEL24_DETECTION_SHTH_0p25G    0x00
#define ACCEL24_DETECTION_SHTH_0p5G     0x10
#define ACCEL24_DETECTION_SHTH_0p75G    0x20
#define ACCEL24_DETECTION_SHTH_1G       0x30
#define ACCEL24_DETECTION_SHTH_1p25G    0x40
#define ACCEL24_DETECTION_SHTH_1p5G     0x50
#define ACCEL24_DETECTION_SHTH_1p75G    0x60
#define ACCEL24_DETECTION_SHTH_2G       0x70
#define ACCEL24_DETECTION_SHTH_MASK     0x70
#define ACCEL24_DETECTION_SHC_8         0x00
#define ACCEL24_DETECTION_SHC_16        0x04
#define ACCEL24_DETECTION_SHC_32        0x08
#define ACCEL24_DETECTION_SHC_64        0x0C
#define ACCEL24_DETECTION_SHC_MASK      0x0C
#define ACCEL24_DETECTION_ORC_16        0x00
#define ACCEL24_DETECTION_ORC_32        0x01
#define ACCEL24_DETECTION_ORC_64        0x02
#define ACCEL24_DETECTION_ORC_128       0x03
#define ACCEL24_DETECTION_ORC_MASK      0x03
#define ACCEL24_DETECTION_NONE          0x00
 
#define ACCEL24_CONTROL_ST              0x80
#define ACCEL24_CONTROL_FSR_2G          0x00
#define ACCEL24_CONTROL_FSR_4G          0x20
#define ACCEL24_CONTROL_FSR_8G          0x40
#define ACCEL24_CONTROL_FSR_UNDEFINED   0x60
#define ACCEL24_CONTROL_FSR_MASK        0x60
#define ACCEL24_CONTROL_PD              0x01
 
#define ACCEL24_ACCEL_RESOLUTION        2048.0f
#define ACCEL24_TEMP_SENSITIVITY        0.586f
#define ACCEL24_TEMP_NOMINAL            25.0f
 
#define ACCEL24_FSR_2G                  0
#define ACCEL24_FSR_4G                  1
#define ACCEL24_FSR_8G                  2
 
#define ACCEL24_WHO_AM_I                0x05
#define ACCEL24_WHO_AM_I_MASK           0x0F
 
#define ACCEL24_DEVICE_ADDRESS          0x15
 
 // accel24_set
 
#define ACCEL24_MAP_MIKROBUS( cfg, mikrobus ) \
    cfg.scl = MIKROBUS( mikrobus, MIKROBUS_SCL ); \
    cfg.sda = MIKROBUS( mikrobus, MIKROBUS_SDA ); \
    cfg.int_pin = MIKROBUS( mikrobus, MIKROBUS_INT )
 
 // accel24_map
 // accel24
 
typedef struct
{
    // Input pins
    digital_in_t int_pin;       
    // Modules
    i2c_master_t i2c;           
    // I2C slave address
    uint8_t slave_address;      
    float fsr_sens;             
} accel24_t;
 
typedef struct
{
    pin_name_t scl;             
    pin_name_t sda;             
    pin_name_t int_pin;         
    uint32_t   i2c_speed;       
    uint8_t    i2c_address;     
} accel24_cfg_t;
 
typedef struct
{
    float x;            
    float y;            
    float z;            
    float temperature;  
} accel24_data_t;
 
typedef enum
{
    ACCEL24_OK = 0,
    ACCEL24_ERROR = -1
 
} accel24_return_value_t;
 
void accel24_cfg_setup ( accel24_cfg_t *cfg );
 
err_t accel24_init ( accel24_t *ctx, accel24_cfg_t *cfg );
 
err_t accel24_default_cfg ( accel24_t *ctx );
 
err_t accel24_generic_write ( accel24_t *ctx, uint8_t reg, uint8_t *data_in, uint8_t len );
 
err_t accel24_generic_read ( accel24_t *ctx, uint8_t reg, uint8_t *data_out, uint8_t len );
 
err_t accel24_write_register ( accel24_t *ctx, uint8_t reg, uint8_t data_in );
 
err_t accel24_read_register ( accel24_t *ctx, uint8_t reg, uint8_t *data_out );
 
err_t accel24_check_communication ( accel24_t *ctx );
 
uint8_t accel24_get_int_pin ( accel24_t *ctx );
 
err_t accel24_soft_reset ( accel24_t *ctx );
 
err_t accel24_set_full_scale_range ( accel24_t *ctx, uint8_t fsr );
 
err_t accel24_read_data ( accel24_t *ctx, accel24_data_t *data_out );
 
#ifdef __cplusplus
}
#endif
#endif // ACCEL24_H
 
 // accel24
 
// ------------------------------------------------------------------------ END