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#define | ADC9_MAP_MIKROBUS(cfg, mikrobus) |
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#define | ADC9_RETVAL uint8_t |
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#define | ADC9_OK 0x00 |
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#define | ADC9_INIT_ERROR 0xFF |
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#define | ADC9_DEVICE_ADR 0x01 |
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#define | ADC9_CMD_DONT_CARE 0x00 |
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#define | ADC9_CMD_STAT_READ 0x01 |
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#define | ADC9_CMD_INC_WRITE 0x02 |
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#define | ADC9_CMD_INC_READ 0x03 |
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#define | ADC9_REG_ADC_DATA 0x00 |
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#define | ADC9_REG_CFG_0 0x01 |
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#define | ADC9_REG_CFG_1 0x02 |
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#define | ADC9_REG_CFG_2 0x03 |
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#define | ADC9_REG_CFG_3 0x04 |
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#define | ADC9_REG_IRQ 0x05 |
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#define | ADC9_REG_MUX 0x06 |
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#define | ADC9_REG_SCAN 0x07 |
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#define | ADC9_REG_TIMER 0x08 |
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#define | ADC9_REG_OFFSET_CAL 0x09 |
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#define | ADC9_REG_GAIN_CAL 0x0A |
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#define | ADC9_RSV_REG_W_A 0x0B |
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#define | ADC9_REG_LOCK 0x0D |
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#define | ADC9_RSV_REG 0x0E |
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#define | ADC9_REG_CRC_CFG 0x0F |
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#define | ADC9_CFG_0_VREF_SEL_0 0x00 |
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#define | ADC9_CFG_0_VREF_SEL_1 0x40 |
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#define | ADC9_CFG_0_VREF_SEL_2 0x80 |
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#define | ADC9_CFG_0_VREF_SEL_3 0xC0 |
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#define | ADC9_CFG_0_CLK_SEL_0 0x00 |
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#define | ADC9_CFG_0_CLK_SEL_1 0x10 |
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#define | ADC9_CFG_0_CLK_SEL_2 0x20 |
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#define | ADC9_CFG_0_CLK_SEL_3 0x30 |
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#define | ADC9_CFG_0_CS_SEL_0 0x00 |
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#define | ADC9_CFG_0_CS_SEL_1 0x04 |
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#define | ADC9_CFG_0_CS_SEL_2 0x08 |
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#define | ADC9_CFG_0_CS_SEL_3 0x0C |
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#define | ADC9_CFG_0_MODE_SHD_DEF 0x00 |
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#define | ADC9_CFG_0_MODE_SHD 0x01 |
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#define | ADC9_CFG_0_MODE_STANDBY 0x02 |
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#define | ADC9_CFG_0_MODE_CONV 0x03 |
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#define | ADC9_CFG_1_PRE_1 0x00 |
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#define | ADC9_CFG_1_PRE_2 0x40 |
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#define | ADC9_CFG_1_PRE_4 0x80 |
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#define | ADC9_CFG_1_PRE_8 0xC0 |
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#define | ADC9_CFG_1_OSR_98304 0x3C |
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#define | ADC9_CFG_1_OSR_81920 0x38 |
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#define | ADC9_CFG_1_OSR_49152 0x34 |
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#define | ADC9_CFG_1_OSR_40960 0x30 |
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#define | ADC9_CFG_1_OSR_24576 0x2C |
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#define | ADC9_CFG_1_OSR_20480 0x28 |
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#define | ADC9_CFG_1_OSR_16384 0x24 |
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#define | ADC9_CFG_1_OSR_8192 0x20 |
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#define | ADC9_CFG_1_OSR_4096 0x1C |
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#define | ADC9_CFG_1_OSR_2048 0x18 |
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#define | ADC9_CFG_1_OSR_1024 0x14 |
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#define | ADC9_CFG_1_OSR_512 0x10 |
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#define | ADC9_CFG_1_OSR_256 0x0C |
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#define | ADC9_CFG_1_OSR_128 0x08 |
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#define | ADC9_CFG_1_OSR_64 0x04 |
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#define | ADC9_CFG_1_OSR_32 0x00 |
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#define | ADC9_CFG_1_DITHER_MAX 0x03 |
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#define | ADC9_CFG_1_DITHER_MED 0x02 |
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#define | ADC9_CFG_1_DITHER_MIN 0x01 |
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#define | ADC9_CFG_1_DITHER_DEF 0x00 |
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#define | ADC9_CFG_2_BOOST_X_2 0xC0 |
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#define | ADC9_CFG_2_BOOST_X_1 0x80 |
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#define | ADC9_CFG_2_BOOST_X_066 0x40 |
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#define | ADC9_CFG_2_BOOST_X_05 0x00 |
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#define | ADC9_CFG_2_GAIN_X_64 0x38 |
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#define | ADC9_CFG_2_GAIN_X_32 0x30 |
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#define | ADC9_CFG_2_GAIN_X_16 0x28 |
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#define | ADC9_CFG_2_GAIN_X_8 0x20 |
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#define | ADC9_CFG_2_GAIN_X_4 0x18 |
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#define | ADC9_CFG_2_GAIN_X_2 0x10 |
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#define | ADC9_CFG_2_GAIN_X_1 0x08 |
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#define | ADC9_CFG_2_GAIN_X_033 0x00 |
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#define | ADC9_CFG_2_AZ_MUX_EN 0x04 |
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#define | ADC9_CFG_2_AZ_MUX_DIS 0x00 |
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#define | ADC9_CFG_2_AZ_VREF_EN 0x02 |
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#define | ADC9_CFG_2_AZ_VREF_DIS 0x00 |
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#define | ADC9_CFG_2_AZ_FREQ_HIGH 0x01 |
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#define | ADC9_CFG_2_AZ_FREQ_LOW 0x00 |
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#define | ADC9_CFG_3_CONV_MODE_CONT 0xC0 |
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#define | ADC9_CFG_3_CONV_MODE_STANDBY 0x80 |
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#define | ADC9_CFG_3_CONV_MODE_SHD 0x40 |
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#define | ADC9_CFG_3_CONV_MODE_SHD0 0x00 |
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#define | ADC9_CFG_3_DATA_FORMAT_CH_ADC 0x30 |
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#define | ADC9_CFG_3_DATA_FORMAT_SIGN_ADC 0x20 |
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#define | ADC9_CFG_3_DATA_FORMAT_LEFT_JUST 0x10 |
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#define | ADC9_CFG_3_DATA_FORMAT_DEF 0x00 |
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#define | ADC9_CFG_3_CRC_FORMAT_32 0x08 |
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#define | ADC9_CFG_3_CRC_FORMAT_16 0x00 |
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#define | ADC9_CFG_3_CRC_COM_EN 0x04 |
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#define | ADC9_CFG_3_CRC_COM_DIS 0x00 |
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#define | ADC9_CFG_3_CRC_OFF_CAL_EN 0x02 |
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#define | ADC9_CFG_3_CRC_OFF_CAL_DIS 0x00 |
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#define | ADC9_CFG_3_CRC_GAIN_CAL_EN 0x01 |
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#define | ADC9_CFG_3_CRC_GAIN_CAL_DIS 0x00 |
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#define | ADC9_IRQ_MODE_MDAT 0x08 |
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#define | ADC9_IRQ_MODE_IRQ 0x00 |
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#define | ADC9_IRQ_MODE_LOGIC_HIGH 0x04 |
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#define | ADC9_IRQ_MODE_HIGH_Z 0x00 |
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#define | ADC9_IRQ_FASTCMD_EN 0x02 |
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#define | ADC9_IRQ_FASTCMD_DIS 0x00 |
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#define | ADC9_IRQ_STP_EN 0x01 |
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#define | ADC9_IRQ_STP_DIS 0x00 |
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#define | ADC9_MUX_VIN_POS_NO_IN 0xF0 |
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#define | ADC9_MUX_VIN_POS_VCM 0xE0 |
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#define | ADC9_MUX_VIN_POS_TEMP 0xD0 |
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#define | ADC9_MUX_VIN_POS_VREF_EXT_MINUS 0xC0 |
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#define | ADC9_MUX_VIN_POS_VREF_EXT_PLUS 0xB0 |
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#define | ADC9_MUX_VIN_POS_VREF_INT 0xA0 |
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#define | ADC9_MUX_VIN_POS_AVDD 0x90 |
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#define | ADC9_MUX_VIN_POS_VSS 0x80 |
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#define | ADC9_MUX_VIN_POS_CH7 0x70 |
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#define | ADC9_MUX_VIN_POS_CH6 0x60 |
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#define | ADC9_MUX_VIN_POS_CH5 0x50 |
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#define | ADC9_MUX_VIN_POS_CH4 0x40 |
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#define | ADC9_MUX_VIN_POS_CH3 0x30 |
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#define | ADC9_MUX_VIN_POS_CH2 0x20 |
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#define | ADC9_MUX_VIN_POS_CH1 0x10 |
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#define | ADC9_MUX_VIN_POS_CH0 0x00 |
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#define | ADC9_MUX_VIN_NEG_NO_IN 0x0F |
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#define | ADC9_MUX_VIN_NEG_VCM 0x0E |
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#define | ADC9_MUX_VIN_NEG_TEMP 0x0D |
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#define | ADC9_MUX_VIN_NEG_VREF_EXT_MINUS 0x0C |
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#define | ADC9_MUX_VIN_NEG_VREF_EXT_PLUS 0x0B |
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#define | ADC9_MUX_VIN_NEG_VREF_INT 0x0A |
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#define | ADC9_MUX_VIN_NEG_AVDD 0x09 |
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#define | ADC9_MUX_VIN_NEG_VSS 0x08 |
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#define | ADC9_MUX_VIN_NEG_CH7 0x07 |
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#define | ADC9_MUX_VIN_NEG_CH6 0x06 |
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#define | ADC9_MUX_VIN_NEG_CH5 0x05 |
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#define | ADC9_MUX_VIN_NEG_CH4 0x04 |
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#define | ADC9_MUX_VIN_NEG_CH3 0x03 |
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#define | ADC9_MUX_VIN_NEG_CH2 0x02 |
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#define | ADC9_MUX_VIN_NEG_CH1 0x01 |
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#define | ADC9_MUX_VIN_NEG_CH0 0x00 |
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#define | ADC9_SCAN_DLY_DM_CLK_X_512 0x00E00000 |
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#define | ADC9_SCAN_DLY_DM_CLK_X_256 0x00C00000 |
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#define | ADC9_SCAN_DLY_DM_CLK_X_128 0x00A00000 |
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#define | ADC9_SCAN_DLY_DM_CLK_X_64 0x00800000 |
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#define | ADC9_SCAN_DLY_DM_CLK_X_32 0x00600000 |
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#define | ADC9_SCAN_DLY_DM_CLK_X_16 0x00400000 |
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#define | ADC9_SCAN_DLY_DM_CLK_X_8 0x00200000 |
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#define | ADC9_SCAN_DLY_NO_DELAY 0x00000000 |
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#define | ADC9_SCAN_PSAV_VREF_OFF 0x00100000 |
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#define | ADC9_SCAN_PSAV_VREF_ON 0x00000000 |
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#define | ADC9_SCAN_OFFSET 0x00008000 |
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#define | ADC9_SCAN_VREF 0x00004000 |
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#define | ADC9_SCAN_AVDD 0x00002000 |
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#define | ADC9_SCAN_TEMP 0x00001000 |
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#define | ADC9_SCAN_DIFF_D 0x00000800 |
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#define | ADC9_SCAN_DIFF_C 0x00000400 |
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#define | ADC9_SCAN_DIFF_B 0x00000200 |
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#define | ADC9_SCAN_DIFF_A 0x00000100 |
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#define | ADC9_SCAN_CH7 0x00000080 |
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#define | ADC9_SCAN_CH6 0x00000040 |
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#define | ADC9_SCAN_CH5 0x00000020 |
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#define | ADC9_SCAN_CH4 0x00000010 |
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#define | ADC9_SCAN_CH3 0x00000008 |
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#define | ADC9_SCAN_CH2 0x00000004 |
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#define | ADC9_SCAN_CH1 0x00000002 |
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#define | ADC9_SCAN_CH0 0x00000001 |
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#define | ADC9_TIMER_DLY_DMCLK_X_16777215 0x00FFFFFF |
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#define | ADC9_TIMER_DLY_DMCLK_X_8388607 0x007FFFFF |
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#define | ADC9_TIMER_DLY_DMCLK_X_4194303 0x003FFFFF |
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#define | ADC9_TIMER_DLY_DMCLK_X_2097151 0x001FFFFF |
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#define | ADC9_TIMER_DLY_DMCLK_X_1048575 0x000FFFFF |
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#define | ADC9_TIMER_DLY_DMCLK_X_524287 0x0007FFFF |
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#define | ADC9_TIMER_DLY_DMCLK_X_262143 0x0003FFFF |
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#define | ADC9_TIMER_DLY_DMCLK_X_131071 0x0001FFFF |
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#define | ADC9_TIMER_DLY_DMCLK_X_65535 0x0000FFFF |
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#define | ADC9_TIMER_DLY_DMCLK_X_32767 0x00007FFF |
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#define | ADC9_TIMER_DLY_DMCLK_X_16383 0x00003FFF |
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#define | ADC9_TIMER_DLY_DMCLK_X_8191 0x00001FFF |
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#define | ADC9_TIMER_DLY_DMCLK_X_4095 0x00000FFF |
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#define | ADC9_TIMER_DLY_DMCLK_X_2047 0x000007FF |
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#define | ADC9_TIMER_DLY_DMCLK_X_1023 0x000003FF |
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#define | ADC9_TIMER_DLY_DMCLK_X_511 0x000001FF |
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#define | ADC9_TIMER_DLY_DMCLK_X_255 0x000000FF |
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#define | ADC9_TIMER_DLY_DMCLK_X_127 0x0000007F |
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#define | ADC9_TIMER_DLY_DMCLK_X_63 0x0000003F |
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#define | ADC9_TIMER_DLY_DMCLK_X_31 0x0000001F |
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#define | ADC9_TIMER_DLY_DMCLK_X_15 0x0000000F |
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#define | ADC9_TIMER_DLY_DMCLK_X_2 0x00000002 |
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#define | ADC9_TIMER_DLY_DMCLK_X_1 0x00000001 |
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#define | ADC9_TIMER_DLY_NO_DELAY 0x00000000 |
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#define | ADC9_FAST_CMD_ADC_CONV_START 0x28 |
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#define | ADC9_FAST_CMD_ADC_STANDBY_MODE 0x2C |
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#define | ADC9_FAST_CMD_ADC_SHUTDOWN_MODE 0x30 |
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#define | ADC9_FAST_CMD_FULL_SHUTDOWN_MODE 0x34 |
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#define | ADC9_FAST_CMD_DEV_FULL_RESET 0x38 |
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#define | ADC9_CALC_COEF 8388608 |
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