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#define | C3DHALL4_REG_0 0x00 |
| 3D Hall 4 register map.
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#define | C3DHALL4_REG_1 0x01 |
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#define | C3DHALL4_REG_2 0x02 |
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#define | C3DHALL4_REG_3 0x03 |
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#define | C3DHALL4_REG_4 0x04 |
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#define | C3DHALL4_REG_5 0x05 |
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#define | C3DHALL4_REG_6 0x06 |
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#define | C3DHALL4_REG_7 0x07 |
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#define | C3DHALL4_REG_PWM_CTRL 0x08 |
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#define | C3DHALL4_REG_CHANNEL_CTRL 0x09 |
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#define | C3DHALL4_REG_OSC_TRIM 0x0A |
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#define | C3DHALL4_REG_THRES_X 0x0B |
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#define | C3DHALL4_REG_THRES_Z 0x0C |
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#define | C3DHALL4_REG_THRES_Y 0x0D |
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#define | C3DHALL4_REG_G_CTRL_X 0x0E |
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#define | C3DHALL4_REG_G_CTRL_Z 0x0F |
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#define | C3DHALL4_REG_G_CTRL_Y 0x10 |
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#define | C3DHALL4_REG_DAC_X 0x11 |
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#define | C3DHALL4_REG_DAC_Z 0x12 |
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#define | C3DHALL4_REG_DAC_Y 0x13 |
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#define | C3DHALL4_REG_SENS_X 0x14 |
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#define | C3DHALL4_REG_SENS_Z 0x15 |
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#define | C3DHALL4_REG_SENS_Y 0x16 |
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#define | C3DHALL4_REG_SENS_TC_X 0x17 |
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#define | C3DHALL4_REG_SENS_TC_Z 0x18 |
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#define | C3DHALL4_REG_SENS_TC_Y 0x19 |
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#define | C3DHALL4_REG_OFFSET_X 0x1A |
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#define | C3DHALL4_REG_OFFSET_Z 0x1B |
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#define | C3DHALL4_REG_OFFSET_Y 0x1C |
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#define | C3DHALL4_REG_OFFSET_TC_X 0x1D |
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#define | C3DHALL4_REG_OFFSET_TC_Z 0x1E |
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#define | C3DHALL4_REG_OFFSET_TC_Y 0x1F |
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#define | C3DHALL4_REG_STATUS 0x3F |
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#define | C3DHALL4_REG_ADC_DATAXL 0x40 |
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#define | C3DHALL4_REG_ADC_DATAXH 0x41 |
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#define | C3DHALL4_REG_ADC_DATAZL 0x42 |
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#define | C3DHALL4_REG_ADC_DATAZH 0x43 |
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#define | C3DHALL4_REG_ADC_DATAYL 0x44 |
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#define | C3DHALL4_REG_ADC_DATAYH 0x45 |
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#define | C3DHALL4_REG_ADC_DATATL 0x46 |
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#define | C3DHALL4_REG_ADC_DATATH 0x47 |
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#define | C3DHALL4_EREG_0 0x00 |
| 3D Hall 4 eeprom map.
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#define | C3DHALL4_EREG_1 0x01 |
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#define | C3DHALL4_EREG_2 0x02 |
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#define | C3DHALL4_EREG_3 0x03 |
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#define | C3DHALL4_EREG_4 0x04 |
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#define | C3DHALL4_EREG_5 0x05 |
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#define | C3DHALL4_EREG_6 0x06 |
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#define | C3DHALL4_EREG_7 0x07 |
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#define | C3DHALL4_EREG_PWM_CTRL 0x08 |
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#define | C3DHALL4_EREG_CHANNEL_CTRL 0x09 |
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#define | C3DHALL4_EREG_OSC_TRIM 0x0A |
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#define | C3DHALL4_EREG_THRES_Y 0x0B |
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#define | C3DHALL4_EREG_THRES_X 0x0C |
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#define | C3DHALL4_EREG_THRES_Z 0x0D |
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#define | C3DHALL4_EREG_GAIN_SEL 0x0E |
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#define | C3DHALL4_EREG_DAC_Y_G0 0x40 |
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#define | C3DHALL4_EREG_DAC_X_G0 0x41 |
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#define | C3DHALL4_EREG_DAC_Z_G0 0x42 |
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#define | C3DHALL4_EREG_SENS_Y_G0 0x43 |
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#define | C3DHALL4_EREG_SENS_X_G0 0x44 |
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#define | C3DHALL4_EREG_SENS_Z_G0 0x45 |
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#define | C3DHALL4_EREG_SENS_TC_Y_G0 0x46 |
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#define | C3DHALL4_EREG_SENS_TC_X_G0 0x47 |
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#define | C3DHALL4_EREG_SENS_TC_Z_G0 0x48 |
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#define | C3DHALL4_EREG_OFFSET_Y_G0 0x49 |
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#define | C3DHALL4_EREG_OFFSET_X_G0 0x4A |
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#define | C3DHALL4_EREG_OFFSET_Z_G0 0x4B |
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#define | C3DHALL4_EREG_OFFSET_TC_Y_G0 0x4C |
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#define | C3DHALL4_EREG_OFFSET_TC_X_G0 0x4D |
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#define | C3DHALL4_EREG_OFFSET_TC_Z_G0 0x4E |
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#define | C3DHALL4_EREG_DAC_Y_G1 0x50 |
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#define | C3DHALL4_EREG_DAC_X_G1 0x51 |
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#define | C3DHALL4_EREG_DAC_Z_G1 0x52 |
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#define | C3DHALL4_EREG_SENS_Y_G1 0x53 |
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#define | C3DHALL4_EREG_SENS_X_G1 0x54 |
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#define | C3DHALL4_EREG_SENS_Z_G1 0x55 |
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#define | C3DHALL4_EREG_SENS_TC_Y_G1 0x56 |
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#define | C3DHALL4_EREG_SENS_TC_X_G1 0x57 |
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#define | C3DHALL4_EREG_SENS_TC_Z_G1 0x58 |
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#define | C3DHALL4_EREG_OFFSET_Y_G1 0x59 |
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#define | C3DHALL4_EREG_OFFSET_X_G1 0x5A |
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#define | C3DHALL4_EREG_OFFSET_Z_G1 0x5B |
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#define | C3DHALL4_EREG_OFFSET_TC_Y_G1 0x5C |
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#define | C3DHALL4_EREG_OFFSET_TC_X_G1 0x5D |
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#define | C3DHALL4_EREG_OFFSET_TC_Z_G1 0x5E |
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#define | C3DHALL4_EREG_DAC_Y_G2 0x60 |
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#define | C3DHALL4_EREG_DAC_X_G2 0x61 |
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#define | C3DHALL4_EREG_DAC_Z_G2 0x62 |
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#define | C3DHALL4_EREG_SENS_Y_G2 0x63 |
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#define | C3DHALL4_EREG_SENS_X_G2 0x64 |
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#define | C3DHALL4_EREG_SENS_Z_G2 0x65 |
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#define | C3DHALL4_EREG_SENS_TC_Y_G2 0x66 |
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#define | C3DHALL4_EREG_SENS_TC_X_G2 0x67 |
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#define | C3DHALL4_EREG_SENS_TC_Z_G2 0x68 |
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#define | C3DHALL4_EREG_OFFSET_Y_G2 0x69 |
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#define | C3DHALL4_EREG_OFFSET_X_G2 0x6A |
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#define | C3DHALL4_EREG_OFFSET_Z_G2 0x6B |
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#define | C3DHALL4_EREG_OFFSET_TC_Y_G2 0x6C |
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#define | C3DHALL4_EREG_OFFSET_TC_X_G2 0x6D |
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#define | C3DHALL4_EREG_OFFSET_TC_Z_G2 0x6E |
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#define | C3DHALL4_EREG_DAC_Y_G3 0x70 |
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#define | C3DHALL4_EREG_DAC_X_G3 0x71 |
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#define | C3DHALL4_EREG_DAC_Z_G3 0x72 |
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#define | C3DHALL4_EREG_SENS_Y_G3 0x73 |
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#define | C3DHALL4_EREG_SENS_X_G3 0x74 |
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#define | C3DHALL4_EREG_SENS_Z_G3 0x75 |
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#define | C3DHALL4_EREG_SENS_TC_Y_G3 0x76 |
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#define | C3DHALL4_EREG_SENS_TC_X_G3 0x77 |
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#define | C3DHALL4_EREG_SENS_TC_Z_G3 0x78 |
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#define | C3DHALL4_EREG_OFFSET_Y_G3 0x79 |
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#define | C3DHALL4_EREG_OFFSET_X_G3 0x7A |
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#define | C3DHALL4_EREG_OFFSET_Z_G3 0x7B |
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#define | C3DHALL4_EREG_OFFSET_TC_Y_G3 0x7C |
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#define | C3DHALL4_EREG_OFFSET_TC_X_G3 0x7D |
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#define | C3DHALL4_EREG_OFFSET_TC_Z_G3 0x7E |
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#define | C3DHALL4_EREG_KEY 0xFE |
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#define | C3DHALL4_EREG_CHECKSUM 0xFF |
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#define | C3DHALL4_CMD_REG_WRITE 0x00 |
| 3D Hall 4 special commands setting.
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#define | C3DHALL4_CMD_REG_READ 0x80 |
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#define | C3DHALL4_CMD_EREG_WRITE 0x01 |
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#define | C3DHALL4_CMD_EREG_READ 0x81 |
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#define | C3DHALL4_CMD_SPECIAL_KEY 0xA5 |
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#define | C3DHALL4_ADC_VREF_3V3 3.3f |
| 3D Hall 4 ADC VREF setting.
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#define | C3DHALL4_ADC_VREF_5V 5.0f |
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#define | C3DHALL4_RANGE_20 0x00 |
| 3D Hall 4 range/sens/offset setting.
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#define | C3DHALL4_RANGE_40 0x01 |
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#define | C3DHALL4_RANGE_350 0x02 |
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#define | C3DHALL4_RANGE_3000 0x03 |
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#define | C3DHALL4_RANGE_MASK 0x03 |
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#define | C3DHALL4_SENS_RANGE_3000 6.0f |
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#define | C3DHALL4_SENS_RANGE_350 60.0f |
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#define | C3DHALL4_SENS_RANGE_40 550.0f |
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#define | C3DHALL4_SENS_RANGE_20 1000.0f |
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#define | C3DHALL4_SENS_TEMPERATURE 168.0f |
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#define | C3DHALL4_OFFSET_XYZ 32768 |
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#define | C3DHALL4_OFFSET_TEMPERATURE 19913 |
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#define | C3DHALL4_SET_DATA_SAMPLE_EDGE SET_SPI_DATA_SAMPLE_EDGE |
| Data sample selection.
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#define | C3DHALL4_SET_DATA_SAMPLE_MIDDLE SET_SPI_DATA_SAMPLE_MIDDLE |
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#define | C3DHALL4_MAP_MIKROBUS(cfg, mikrobus) |
| MikroBUS pin mapping.
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